A method and apparatus for mitigating electromagnetic noise in an electronic device. The method includes generating a trigger clock signal at a first frequency, and generating a second clock signal at a second frequency. The second frequency is higher than the first frequency. The method also includes receiving an input signal with a converter circuit, detecting an event based on the trigger clock signal, and predicting a time for a conversion of the input signal based on the detected event. The method further includes blanking the second clock signal for a predetermined period based on the predicted time for a conversion.

A duty correction circuit may be provided. The duty correction circuit may include a control circuit configured to generate a duty correction control signal by detecting edges of first and second differential clock signals. The duty a duty correction clock signal generation circuit may be configured to generate a duty correction clock signal according to edges of the duty correction control signal.

A duty correction circuit may be provided. The duty correction circuit may include a control circuit configured to generate a duty correction control signal by detecting edges of first and second differential clock signals. The duty a duty correction clock signal generation circuit may be configured to generate a duty correction clock signal according to edges of the duty correction control signal.

An analog signal is accurately converted into a digital signal. An oscillator generates an oscillation signal having a cycle that depends on a signal level of an input analog signal. A current bit generation unit generates, as a current bit, a bit indicating a value of the oscillation signal at each of a plurality of timings within the cycle. A delay unit delays each current bit over a predetermined period and supplies the delayed current bit as a delayed bit. A determination unit determines whether a change amount of a phase of the oscillation signal changed within the predetermined period is greater than a half cycle of the cycle. An output unit generates and outputs data indicating a period in which respective values of the current bit and the delayed bit form a specific combination when the change amount is not greater than the half cycle, and generates and outputs data indicating a period in which the respective values of the current bit and the delayed bit are the same or form the specific combination when the change amount is greater than the half cycle.

An analog signal is accurately converted into a digital signal. An oscillator generates an oscillation signal having a cycle that depends on a signal level of an input analog signal. A current bit generation unit generates, as a current bit, a bit indicating a value of the oscillation signal at each of a plurality of timings within the cycle. A delay unit delays each current bit over a predetermined period and supplies the delayed current bit as a delayed bit. A determination unit determines whether a change amount of a phase of the oscillation signal changed within the predetermined period is greater than a half cycle of the cycle. An output unit generates and outputs data indicating a period in which respective values of the current bit and the delayed bit form a specific combination when the change amount is not greater than the half cycle, and generates and outputs data indicating a period in which the respective values of the current bit and the delayed bit are the same or form the specific combination when the change amount is greater than the half cycle.

An encoder for modulating data on level transitions of a signal transmitted on a wired communication channel to increase channel data throughput, comprising a circuitry configured for receiving a signal transmitted by a transmitting communication node, the signal carries a message to one or more receiving communication nodes connected to a wired communication channel, calculating a respective delay period consisting of a number of delay time units encoding one or more data items, delaying one or more transitions of a waveform level of the signal by the respective delay period to modulate the signal to carry the data item(s) and transmitting the modulated signal to one or more of the receiving communication nodes having a decoder configured for demodulating the modulated signal.

An encoder for modulating data on level transitions of a signal transmitted on a wired communication channel to increase channel data throughput, comprising a circuitry configured for receiving a signal transmitted by a transmitting communication node, the signal carries a message to one or more receiving communication nodes connected to a wired communication channel, calculating a respective delay period consisting of a number of delay time units encoding one or more data items, delaying one or more transitions of a waveform level of the signal by the respective delay period to modulate the signal to carry the data item(s) and transmitting the modulated signal to one or more of the receiving communication nodes having a decoder configured for demodulating the modulated signal.

According to one embodiment, a synchronous semiconductor device is disclosed According to this embodiment, the synchronous semiconductor device includes a pulse width detection circuit to determine whether at least one of a plurality of delay step sizes is less than at least one of a high pulse width and a low pulse width of a first clock signal and to select one of the delay step sizes and a delay line to delay the first clock signal to produce as second clock signal by a first delay amount that is changed based at least on the one of the delay step sizes.

According to one embodiment, a synchronous semiconductor device is disclosed According to this embodiment, the synchronous semiconductor device includes a pulse width detection circuit to determine whether at least one of a plurality of delay step sizes is less than at least one of a high pulse width and a low pulse width of a first clock signal and to select one of the delay step sizes and a delay line to delay the first clock signal to produce as second clock signal by a first delay amount that is changed based at least on the one of the delay step sizes.

An apparatus includes a phase modulator configured to modulate a phase of an incoming frequency-modulated signal based on a clock signal to generate a phase-modulated signal, where the clock signal is associated with a clock frequency. The apparatus also includes an etalon configured to receive the phase-modulated signal and generate an output signal based on the phase-modulated signal. The apparatus further includes a detector configured to identify amplitudes associated with a first harmonic of the clock frequency and a first subharmonic of the clock frequency in the output signal. In addition, the apparatus includes a decoder configured to recover information encoded in the incoming frequency-modulated signal based on instantaneous frequency deviations of the incoming frequency-modulated signal, where the instantaneous frequency deviations are identified based on relative amplitudes of the first harmonic and the first subharmonic.