An apparatus includes a phase modulator configured to modulate a phase of an incoming frequency-modulated signal based on a clock signal to generate a phase-modulated signal, where the clock signal is associated with a clock frequency. The apparatus also includes an etalon configured to receive the phase-modulated signal and generate an output signal based on the phase-modulated signal. The apparatus further includes a detector configured to identify amplitudes associated with a first harmonic of the clock frequency and a first subharmonic of the clock frequency in the output signal. In addition, the apparatus includes a decoder configured to recover information encoded in the incoming frequency-modulated signal based on instantaneous frequency deviations of the incoming frequency-modulated signal, where the instantaneous frequency deviations are identified based on relative amplitudes of the first harmonic and the first subharmonic.

A circuit is provided for ringing suppression. The circuit comprises a termination resistor coupled to a bus via a switch; and a control circuit. The control circuit comprises an input coupled to a data input pin of a bus transceiver and an output coupled to control the termination resistor. The circuit is configured to selectively couple the resistor to the bus in response to a transition on the input bit stream.

A circuit is provided for ringing suppression. The circuit comprises a termination resistor coupled to a bus via a switch; and a control circuit. The control circuit comprises an input coupled to a data input pin of a bus transceiver and an output coupled to control the termination resistor. The circuit is configured to selectively couple the resistor to the bus in response to a transition on the input bit stream.

The present technology relates to a signal processing apparatus and a signal processing method that allow easy adjustment of a pulse duty ratio.

A phase comparison section outputs a phase difference signal corresponding to a phase difference between rising edges or falling edges of a first pulse and a second pulse. The first pulse is used as a basis at the time of adjusting a duty ratio, and the second pulse has a duty ratio that is to be adjusted. A reference signal generation section outputs a reference signal that starts changing according to the first pulse. A comparison section outputs a comparison output signal representing a magnitude relation between the phase difference signal and the reference signal, and the comparison output signal is fed back as the second pulse. The present technology is applicable to a case of adjusting a duty ratio of a pulse.

The invention relates to a method for determining a time of a flank in a signal, wherein the method comprises a step of reading the signal and has a master clock rate for operating a digital evaluation unit for evaluating the time of the flank. The method also comprises a step of forming a data word representing the signal, using a deserializer of a SERDES cell, wherein the data word has a plurality of bits, and wherein a sampling clock rate is applied to the SERDES cell for sampling the signal, which sampling clock rate is higher than the master clock rate, wherein one flank or two flanks of the sampling clock rate are used for sampling the signal. Finally, the method comprises a step of determining the time of the flank in the signal using the data word and the master clock rate in the evaluation unit.

The invention relates to a method for determining a time of a flank in a signal, wherein the method comprises a step of reading the signal and has a master clock rate for operating a digital evaluation unit for evaluating the time of the flank. The method also comprises a step of forming a data word representing the signal, using a deserializer of a SERDES cell, wherein the data word has a plurality of bits, and wherein a sampling clock rate is applied to the SERDES cell for sampling the signal, which sampling clock rate is higher than the master clock rate, wherein one flank or two flanks of the sampling clock rate are used for sampling the signal. Finally, the method comprises a step of determining the time of the flank in the signal using the data word and the master clock rate in the evaluation unit.

A delay measurement circuit includes a first skew circuit disposed proximate to a first bonding pad configured to receive a first clock signal having a first frequency. The delay measurement circuit includes a second skew circuit disposed proximate to a second bonding pad configured to receive a second clock signal having a second frequency. The first and second skew circuits each have a first mode of operation as zero-delay-return path and a second mode of operation as a synchronized pass path. The delay measurement circuit includes a pair of conductive traces coupled to the first skew circuit, another pair of conductive traces coupled to the second skew circuit, a time-to-digital converter circuit, and a switch circuit configured to selectively couple the time-to-digital converter circuit to the first skew circuit via the pair of conductive traces and the second skew circuit via the other pair of conductive traces.

A delay measurement circuit includes a first skew circuit disposed proximate to a first bonding pad configured to receive a first clock signal having a first frequency. The delay measurement circuit includes a second skew circuit disposed proximate to a second bonding pad configured to receive a second clock signal having a second frequency. The first and second skew circuits each have a first mode of operation as zero-delay-return path and a second mode of operation as a synchronized pass path. The delay measurement circuit includes a pair of conductive traces coupled to the first skew circuit, another pair of conductive traces coupled to the second skew circuit, a time-to-digital converter circuit, and a switch circuit configured to selectively couple the time-to-digital converter circuit to the first skew circuit via the pair of conductive traces and the second skew circuit via the other pair of conductive traces.

An apparatus for analyzing currents in an electric load is provided with a current measuring circuit, which can be connected in series with the parallel circuit of the load branches, and a detector for detecting a change in the current when the switching element in a load branch is switched on or off. The apparatus also has an analysis unit which is connected to the control unit and to the detector and analyzes the temporal correlation of a control signal for switching a switching element in a load branch on or off with the detection of the change in the current and/or analyzes the change in the current at a plurality of times of switching a relevant switching element in a load branch or the switching elements in a plurality of load branches.

An electronic device includes: a first equalizing circuit configured to receive a data signal and output a first equalizing signal based on the data signal; a pulse generator configured to generate a first pulse signal and a second pulse signal in response to a rising edge and a falling edge of the data signal, respectively; a second equalizing circuit configured to output a second equalizing signal based on the first pulse signal and the second pulse signal that have been inverted; and an output terminal configured to output an output signal in which the first equalizing signal and the second equalizing signal have been summed.