A circuit assembly for monitoring a sinusoidal alternating voltage signal having a comparing element receiving at an input the signal with period T and generating a first output signal at an output based upon the signal exceeding a threshold; a zero crossing detector receives at its input the signal and generates a output signal at its output; a timing element connected to zero crossing detector generates a clock signal dependent on the second output signal; and a flip-flop. The comparing element output is connected to a state-controlled input of the flip-flop and the timing element output is connected to an edge-controlled input of the flip-flop. The flip-flop generates a state signal at its output. The timing element specifies a state change of the clock signal at an instant that differs from the instant at T/4 after a zero crossing of the signal.

A circuit assembly for monitoring a sinusoidal alternating voltage signal having a comparing element receiving at an input the signal with period T and generating a first output signal at an output based upon the signal exceeding a threshold; a zero crossing detector receives at its input the signal and generates a output signal at its output; a timing element connected to zero crossing detector generates a clock signal dependent on the second output signal; and a flip-flop. The comparing element output is connected to a state-controlled input of the flip-flop and the timing element output is connected to an edge-controlled input of the flip-flop. The flip-flop generates a state signal at its output. The timing element specifies a state change of the clock signal at an instant that differs from the instant at T/4 after a zero crossing of the signal.

A low latency comparator circuit with a local clock circuit is disclosed. A comparator circuit configured to compare a first input signal to a second input signal. The comparator circuit includes at least one regenerative latch circuit having a first and second inputs configured to receive the first and second input signals, respectively. The comparator circuit further includes a clock circuit configured to generate and provide a clock signal exclusively to circuitry in the comparator circuit, including the at least one regenerative latch circuit. At least one output latch circuit coupled to the at least one regenerative latch circuit and configured to provide a first output signal indicative of a comparison of the first and second input signals.

A zero-crossing detection circuit includes a zero-crossing detection unit arranged to compare a first monitoring target signal and a second monitoring target signal respectively input through diodes from a first node and a second node between which an AC signal is applied, so as to generate a first comparison signal, and a logic unit arranged to estimate a zero cross of the AC signal from the first comparison signal so as to generate a zero-crossing detection signal. The zero-crossing detection circuit preferably includes a monitoring unit arranged to adjust the first monitoring target signal and the second monitoring target signal to be suitable for input to the zero-crossing detection unit. The logic unit preferably counts a period of the first comparison signal and estimates a zero cross of the AC signal using a count value thereof.

A zero-crossing detection circuit includes a zero-crossing detection unit arranged to compare a first monitoring target signal and a second monitoring target signal respectively input through diodes from a first node and a second node between which an AC signal is applied, so as to generate a first comparison signal, and a logic unit arranged to estimate a zero cross of the AC signal from the first comparison signal so as to generate a zero-crossing detection signal. The zero-crossing detection circuit preferably includes a monitoring unit arranged to adjust the first monitoring target signal and the second monitoring target signal to be suitable for input to the zero-crossing detection unit. The logic unit preferably counts a period of the first comparison signal and estimates a zero cross of the AC signal using a count value thereof.

A zero-crossing detection circuit includes a zero-crossing detection unit arranged to compare a first monitoring target signal and a second monitoring target signal respectively input through diodes from a first node and a second node between which an AC signal is applied, so as to generate a first comparison signal, and a logic unit arranged to estimate a zero cross of the AC signal from the first comparison signal so as to generate a zero-crossing detection signal. The zero-crossing detection circuit preferably includes a monitoring unit arranged to adjust the first monitoring target signal and the second monitoring target signal to be suitable for input to the zero-crossing detection unit. The logic unit preferably counts a period of the first comparison signal and estimates a zero cross of the AC signal using a count value thereof.

A zero-crossing detection circuit includes a zero-crossing detection unit arranged to compare a first monitoring target signal and a second monitoring target signal respectively input through diodes from a first node and a second node between which an AC signal is applied, so as to generate a first comparison signal, and a logic unit arranged to estimate a zero cross of the AC signal from the first comparison signal so as to generate a zero-crossing detection signal. The zero-crossing detection circuit preferably includes a monitoring unit arranged to adjust the first monitoring target signal and the second monitoring target signal to be suitable for input to the zero-crossing detection unit. The logic unit preferably counts a period of the first comparison signal and estimates a zero cross of the AC signal using a count value thereof.

The present disclosure relates to an edge detection circuit configured to receive an input signal comprising one or more falling or falling edges and provide an output signal comprising pulses or spikes corresponding to the one or more rising or falling edges. The edge detection circuit comprises a passive differentiator circuit configured to receive an input and provide a differentiator output signal that that is proportional to the rate of change of the input, and a comparator circuit operably connected to a voltage source. The comparator circuit is configured to receive the differentiator output signal, compare the differentiator output signal to a threshold voltage; and output a pulse or spike signal based on the comparison to the threshold voltage.

The present disclosure relates to an edge detection circuit configured to receive an input signal comprising one or more falling or falling edges and provide an output signal comprising pulses or spikes corresponding to the one or more rising or falling edges. The edge detection circuit comprises a passive differentiator circuit configured to receive an input and provide a differentiator output signal that that is proportional to the rate of change of the input, and a comparator circuit operably connected to a voltage source. The comparator circuit is configured to receive the differentiator output signal, compare the differentiator output signal to a threshold voltage; and output a pulse or spike signal based on the comparison to the threshold voltage.

A spread spectrum clock generation device that may reduce electromagnetic interference (EMI) includes: a first comparator configured to compare an input signal with a first reference voltage and output a first comparison signal; a second comparator configured to compare the input signal with a second reference voltage and output a second comparison signal; a latch configured to receive the first and second comparison signals as inputs and output an output signal; and a delaying circuit configured to generate the input signal by delaying the output signal to have a different delay time for each time interval.