Methods, systems, and devices for controlling a variable capacitor. One aspect features a variable capacitance device that includes a capacitor, a first transistor, a second transistor, and control circuitry. The control circuitry is configured to adjust an effective capacitance of the capacitor by performing operations including detecting a zero-crossing of an input current at a first time. Switching off the first transistor. Estimating a first delay period for switching the first transistor on when a voltage across the capacitor is zero. Switching on the first transistor after the first delay period from the first time. Detecting a zero-crossing of the input current at a second time. Switching off the second transistor. Estimating a second delay period for switching the second transistor on when a voltage across the capacitor is zero. Switching on the second transistor after the second delay period from the second time.

Methods, systems, and devices for controlling a variable capacitor. One aspect features a variable capacitance device that includes a capacitor, a first transistor, a second transistor, and control circuitry. The control circuitry is configured to adjust an effective capacitance of the capacitor by performing operations including detecting a zero-crossing of an input current at a first time. Switching off the first transistor. Estimating a first delay period for switching the first transistor on when a voltage across the capacitor is zero. Switching on the first transistor after the first delay period from the first time. Detecting a zero-crossing of the input current at a second time. Switching off the second transistor. Estimating a second delay period for switching the second transistor on when a voltage across the capacitor is zero. Switching on the second transistor after the second delay period from the second time.

A relay circuit, including a solid state relay switch, connected to a first relay line and to a charging capacitor, and connected to a second relay line. The relay circuit may also include a solid state relay control circuit, coupled between the charging capacitor and the solid state relay switch. The solid state relay control circuit may include a voltage detection circuit, having an input coupled to an output of the charging capacitor, and having an output arranged to generate a LOW voltage signal when a voltage level of the charging capacitor is below a low threshold value. The solid state relay control circuit may also include a zero crossing circuit, coupled to the first relay line and the second relay line, and having an output to generate a clock signal when a zero crossing event takes place between the first relay line and the second relay line.

A zero-crossing detection circuit includes a logic unit and an input stop detection unit. The logic unit is configured to estimate a zero cross of an AC signal in accordance with at least one of a first monitoring target signal and a second monitoring target signal, respectively input through diodes from a first node and a second node between which the AC signal is applied, so as to generate a zero-crossing detection signal. The input stop detection unit is configured to compare the first monitoring target signal with the second monitoring target signal after giving an offset to one of them so as to generate an input stop detection signal. The logic unit is configured to fix a logic level of the zero-crossing detection signal in accordance with the input stop detection signal.

A zero-crossing detection circuit includes a logic unit and an input stop detection unit. The logic unit is configured to estimate a zero cross of an AC signal in accordance with at least one of a first monitoring target signal and a second monitoring target signal, respectively input through diodes from a first node and a second node between which the AC signal is applied, so as to generate a zero-crossing detection signal. The input stop detection unit is configured to compare the first monitoring target signal with the second monitoring target signal after giving an offset to one of them so as to generate an input stop detection signal. The logic unit is configured to fix a logic level of the zero-crossing detection signal in accordance with the input stop detection signal.

A zero-cross detection device includes: an input terminal configured to receive an input voltage via a diode from an application terminal for an alternating-current voltage relative to a reference potential; an input circuit including a resistor between the input terminal and a terminal at the reference potential; a period detection circuit configured to detect the length of the period of the alternating-current voltage based on the interval of the timings at which the input voltage exceeds a threshold voltage; a peak detection circuit configured to detect the peak timing at which the input voltage reaches a peak in each period of the alternating-current voltage; and a zero-cross timing detection circuit configured to detect the zero-cross timing of the alternating-current voltage based on the results of detection by the period detection circuit and the peak detection circuit.

A zero-cross detection device includes: an input terminal configured to receive an input voltage via a diode from an application terminal for an alternating-current voltage relative to a reference potential; an input circuit including a resistor between the input terminal and a terminal at the reference potential; a period detection circuit configured to detect the length of the period of the alternating-current voltage based on the interval of the timings at which the input voltage exceeds a threshold voltage; a peak detection circuit configured to detect the peak timing at which the input voltage reaches a peak in each period of the alternating-current voltage; and a zero-cross timing detection circuit configured to detect the zero-cross timing of the alternating-current voltage based on the results of detection by the period detection circuit and the peak detection circuit.

An ANC system is provided, including an AD converter performing an AD conversion on an external noise signal; an ANC signal generator generating an ANC signal for canceling a noise component arriving at ears of a user based on an output signal of the AD converter; a level detector detecting a level of the output signal and causes the ANC signal generator to power down in response to the level; and a zero-cross detector detecting a zero-cross timing of the ANC signal. The level detector starts measuring a time when the level is equal to or less than a first threshold value, and causes the ANC signal generator to perform a power down operation when the zero-cross timing is detected after the measured time exceeds the predetermined value, and causes the ANC signal generator to exit from the power down operation when the level exceeds a second threshold value.

An ANC system is provided, including an AD converter performing an AD conversion on an external noise signal; an ANC signal generator generating an ANC signal for canceling a noise component arriving at ears of a user based on an output signal of the AD converter; a level detector detecting a level of the output signal and causes the ANC signal generator to power down in response to the level; and a zero-cross detector detecting a zero-cross timing of the ANC signal. The level detector starts measuring a time when the level is equal to or less than a first threshold value, and causes the ANC signal generator to perform a power down operation when the zero-cross timing is detected after the measured time exceeds the predetermined value, and causes the ANC signal generator to exit from the power down operation when the level exceeds a second threshold value.

A low latency comparator circuit with a local clock circuit is disclosed. A comparator circuit configured to compare a first input signal to a second input signal. The comparator circuit includes at least one regenerative latch circuit having a first and second inputs configured to receive the first and second input signals, respectively. The comparator circuit further includes a clock circuit configured to generate and provide a clock signal exclusively to circuitry in the comparator circuit, including the at least one regenerative latch circuit. At least one output latch circuit coupled to the at least one regenerative latch circuit and configured to provide a first output signal indicative of a comparison of the first and second input signals.