A circuit assembly for monitoring a sinusoidal alternating voltage signal having a comparing element receiving at an input the signal with period T and generating a first output signal at an output based upon the signal exceeding a threshold; a zero crossing detector receives at its input the signal and generates a output signal at its output; a timing element connected to zero crossing detector generates a clock signal dependent on the second output signal; and a flip-flop. The comparing element output is connected to a state-controlled input of the flip-flop and the timing element output is connected to an edge-controlled input of the flip-flop. The flip-flop generates a state signal at its output. The timing element specifies a state change of the clock signal at an instant that differs from the instant at T/4 after a zero crossing of the signal.

A circuit assembly for monitoring a sinusoidal alternating voltage signal having a comparing element receiving at an input the signal with period T and generating a first output signal at an output based upon the signal exceeding a threshold; a zero crossing detector receives at its input the signal and generates a output signal at its output; a timing element connected to zero crossing detector generates a clock signal dependent on the second output signal; and a flip-flop. The comparing element output is connected to a state-controlled input of the flip-flop and the timing element output is connected to an edge-controlled input of the flip-flop. The flip-flop generates a state signal at its output. The timing element specifies a state change of the clock signal at an instant that differs from the instant at T/4 after a zero crossing of the signal.

An ANC system includes an AD converter which performs AD conversion on an external noise signal, an ANC signal generator which generates an ANC signal for canceling a noise component arriving at the ears of a user based on an output signal of the AD converter, and a level detector which detects a level of the output signal and causes the ANC signal generator to power down in response to the level. The level detector measures a time for which the level is equal to or less than a predetermined first threshold value, causes the ANC signal generator or a portion of blocks of the AD converter to power down after the measured time exceeds a predetermined value, and causes the ANC signal generator or a portion of blocks of the AD converter to return from the power down when the level exceeds a predetermined second threshold value.

An ANC system includes an AD converter which performs AD conversion on an external noise signal, an ANC signal generator which generates an ANC signal for canceling a noise component arriving at the ears of a user based on an output signal of the AD converter, and a level detector which detects a level of the output signal and causes the ANC signal generator to power down in response to the level. The level detector measures a time for which the level is equal to or less than a predetermined first threshold value, causes the ANC signal generator or a portion of blocks of the AD converter to power down after the measured time exceeds a predetermined value, and causes the ANC signal generator or a portion of blocks of the AD converter to return from the power down when the level exceeds a predetermined second threshold value.

A method of monitoring the condition of a circuit comprises establishing a known baseline signal for a type of circuit (each is somewhat different) and defining these characteristics in terms of the lead and trailing edge angular components (@ zero crossing point), the voltage (amplitude), and the period (time length) of the waveform. Ideally, the angular component of the square wave should be vertical, or at 90 degrees to x-axis. The baseline non-regular square wave that is composed of current, voltage, any harmonic thereof, or the combination of these signals which best indicate predictive measurement attributed to the type of circuit being monitored. Future wave forms indicate the rate of decay based upon the aggregated angular, amplitude, and period components of the zero-crossing points when compared to the baseline signal and/or prior waveform of the observed specific splice. The rate of decay can help determine the life expectancy of the circuit.

A method of monitoring the condition of a circuit comprises establishing a known baseline signal for a type of circuit (each is somewhat different) and defining these characteristics in terms of the lead and trailing edge angular components (@ zero crossing point), the voltage (amplitude), and the period (time length) of the waveform. Ideally, the angular component of the square wave should be vertical, or at 90 degrees to x-axis. The baseline non-regular square wave that is composed of current, voltage, any harmonic thereof, or the combination of these signals which best indicate predictive measurement attributed to the type of circuit being monitored. Future wave forms indicate the rate of decay based upon the aggregated angular, amplitude, and period components of the zero-crossing points when compared to the baseline signal and/or prior waveform of the observed specific splice. The rate of decay can help determine the life expectancy of the circuit.

A primary side wireless power transmitter inductively couplable to a secondary side wireless power receiver for supplying power to the wireless power receiver for receiving communications from the secondary side wireless power receiver through the inductive coupling comprises a primary side tank circuit receiving a signal on from the secondary side wireless power receiver. A phase delay or time delay circuit generates a fixed delay clock signal. A sample and hold circuit samples a tank circuit voltage utilizing the fixed phase or time delayed clock signal. A comparator is coupled to an output of the sample and hold circuit for extracting data or commands from the signal stream. A method of operating a primary side wireless transmitter inductively coupled to a secondary side wireless power receiver for supplying power to the wireless power receiver to power a load coupled to the receiver is also disclosed.

A primary side wireless power transmitter inductively couplable to a secondary side wireless power receiver for supplying power to the wireless power receiver for receiving communications from the secondary side wireless power receiver through the inductive coupling comprises a primary side tank circuit receiving a signal on from the secondary side wireless power receiver. A phase delay or time delay circuit generates a fixed delay clock signal. A sample and hold circuit samples a tank circuit voltage utilizing the fixed phase or time delayed clock signal. A comparator is coupled to an output of the sample and hold circuit for extracting data or commands from the signal stream. A method of operating a primary side wireless transmitter inductively coupled to a secondary side wireless power receiver for supplying power to the wireless power receiver to power a load coupled to the receiver is also disclosed.

The present disclosure provides a control circuit, where the control circuit includes: a signal detection unit, a zero-crossing detection (ZCD) signal acquisition unit, a pulse width modulation (PWM) control signal generation unit, and a signal processing unit; where the signal detection unit, the ZCD signal acquisition unit, the PWM control signal generation unit and the signal processing unit are connected in cascade. The control circuit provided in the present disclosure reduces processing delay of a ZCD signal and improve signal a processing accuracy of a power factor correction (PFC) system.

The present disclosure provides a control circuit, where the control circuit includes: a signal detection unit, a zero-crossing detection (ZCD) signal acquisition unit, a pulse width modulation (PWM) control signal generation unit, and a signal processing unit; where the signal detection unit, the ZCD signal acquisition unit, the PWM control signal generation unit and the signal processing unit are connected in cascade. The control circuit provided in the present disclosure reduces processing delay of a ZCD signal and improve signal a processing accuracy of a power factor correction (PFC) system.