A control circuit regulates the propagation delay of a field effect transistor (FET) before the FET transitions to the Miller region by applying a pre-charge current for a fixed duration to the gates of the FET. After the fixed duration, the current is reduced to a lower drive current level which is based on a desired output voltage slew rate. After the FET transitions to the Miller region, the output voltage slews down in accordance with the output voltage slew rate. By regulating the slew-rate of the output voltage in the Miller region and regulating the propagation delay of the FET prior to the Miller region, the control circuit reduces electromagnetic interference (EMI) caused by the switching of the FET, thereby improving electromagnetic compatibility (EMC) of switch mode driver systems without increasing the propagation delay of the FET.

A method is provided for driving a half bridge circuit that includes a first transistor and a second transistor that are switched in a complementary manner. The method includes generating an off-current during a plurality of turn-off switching events to control a gate voltage of the second transistor; measuring a transistor parameter of the second transistor during a first turn-off switching event during which the second transistor is transitioned to an off state, wherein the transistor parameter is indicative of an oscillation at the first transistor during a corresponding turn-on switching event during which the first transistor is transitioned to an on state; and activating a portion of the off-current for the second turn-off switching event, including regulating an interval length of the second portion for the second turn-off switching event based on the measured transistor parameter measured during the first turn-off switching event.

A method is provided for driving a half bridge circuit that includes a first transistor and a second transistor that are switched in a complementary manner. The method includes generating an off-current during a plurality of turn-off switching events to control a gate voltage of the second transistor; measuring a transistor parameter of the second transistor during a first turn-off switching event during which the second transistor is transitioned to an off state, wherein the transistor parameter is indicative of an oscillation at the first transistor during a corresponding turn-on switching event during which the first transistor is transitioned to an on state; and activating a portion of the off-current for the second turn-off switching event, including regulating an interval length of the second portion for the second turn-off switching event based on the measured transistor parameter measured during the first turn-off switching event.

Circuits and methods for reducing lagging responses of a power converter to changes in circuit voltages or current, over-shoot/under-shoot when a target output voltage changes faster than the power converter's response, and open loop conditions. Embodiments include scanning a feedback voltage from a load powered by a voltage output by a power converter controlled by a PWM control signal; detecting an under-regulation condition; and, while the under-regulation condition is detected, increasing a clock signal rate to a counter outputting a count value usable to generate the PWM control signal. Embodiments include comparing a target output voltage to a signal representative of an output voltage of the power converter; indicating an under-shoot or over-shoot condition if the voltage difference exceeds a corresponding offset value; and limiting the range of values for an M-bit count value used to generate the PWM control signal to mitigate the under-shoot or over-shoot condition.

Circuits and methods for reducing lagging responses of a power converter to changes in circuit voltages or current, over-shoot/under-shoot when a target output voltage changes faster than the power converter's response, and open loop conditions. Embodiments include scanning a feedback voltage from a load powered by a voltage output by a power converter controlled by a PWM control signal; detecting an under-regulation condition; and, while the under-regulation condition is detected, increasing a clock signal rate to a counter outputting a count value usable to generate the PWM control signal. Embodiments include comparing a target output voltage to a signal representative of an output voltage of the power converter; indicating an under-shoot or over-shoot condition if the voltage difference exceeds a corresponding offset value; and limiting the range of values for an M-bit count value used to generate the PWM control signal to mitigate the under-shoot or over-shoot condition.

A synchronous rectifier includes: an integrator configured to integrate a voltage across a secondary side winding of a transformer over an integral period having an expected zero integral value; a first comparator configured to detect an end of a demagnetization phase of the secondary side winding based on diode detection; and a digital circuit configured to adjust a channel gain of the synchronous rectifier based on an integration error at the end of the integral period, the integration error corresponding to the difference between the integrated voltage at the end of the integral period and the expected zero integral. Corresponding methods of gain tuning and a power converter are also described.

A synchronous rectifier includes: an integrator configured to integrate a voltage across a secondary side winding of a transformer over an integral period having an expected zero integral value; a first comparator configured to detect an end of a demagnetization phase of the secondary side winding based on diode detection; and a digital circuit configured to adjust a channel gain of the synchronous rectifier based on an integration error at the end of the integral period, the integration error corresponding to the difference between the integrated voltage at the end of the integral period and the expected zero integral. Corresponding methods of gain tuning and a power converter are also described.

This invention, is concerning a signal voltage device, in which transformers 22a, 22b and a reception circuit 24 are formed on the same chip, and accordingly, no ESD protective element connected to a transformer connection terminal of the reception circuit 24 is required, and negative pulses generated in reception-side inductors 11 can be used in signal transmission. Signal transmission using both positive pulses and negative pulses is made possible as a result, and a stable signal transmission operation can be carried out even in a case where delay time varies in a signal detection circuit. Further, a reception circuit of low power consumption can be configured by using a single-ended Schmitt trigger circuit 14 in the signal detection circuit.

The present disclosure relates to a comparator, an AD converter, a solid-state image pickup device, an electronic device, a method of controlling the comparator, a data writing circuit, a data reading circuit, and a data transferring circuit, capable of improving the determining speed of the comparator and reducing power consumption. The comparator includes: a differential input circuit configured to operate with a first power supply voltage, the differential input circuit configured to output a signal when an input signal is higher than a reference signal in voltage; a positive feedback circuit configured to operate with a second power supply voltage lower than the first power supply voltage, the positive feedback circuit being configured to accelerate transition speed when a compared result signal indicating a compared result between the input signal and the reference signal in voltage, is inverted, on the basis of the output signal of the differential input circuit; and a voltage conversion circuit configured to convert the output signal of the differential input circuit into a signal corresponding to the second power supply voltage. The present disclosure can be applied to, for example, a comparator of a solid-state image pickup device.

A power semiconductor module includes at least one upper arm provided between a positive electrode line and a node and including a power semiconductor device and a freewheeling diode connected in parallel, at least one lower arm provided between a negative electrode line and the node and including a power semiconductor device and a freewheeling diode connected in parallel, and a snubber circuit provided between the positive electrode line and the negative electrode line. The snubber circuit includes a snubber capacitor and a snubber resistor connected in series. At least one control terminal outputs a voltage representing the temperature of the snubber resistor or a voltage related to the temperature of the snubber resistor to a driver that drives the power semiconductor device.