In a method of repairing through-electrodes, a plurality of through-electrodes are grouped into a plurality of through-electrode groups. A plurality of redundant through-electrodes are grouped into a plurality of redundant through-electrode groups. Repair paths for the plurality of through-electrodes are searched. When searching the repair paths, in response to a Y-th through-electrode included in an X-th through-electrode group being a defective through-electrode or in response to receiving a first signal from an (X−1)-th through-electrode group, it is determined whether a y-th redundant through-electrode included in an x-th redundant through-electrode group is available for performing signal transmission thereto. In response to the y-th redundant through-electrode being available for performing signal transmission thereto, a second signal input to the Y-th through-electrode is transmitted to the y-th redundant through-electrode. In response to the y-th redundant through-electrode being unavailable for performing signal transmission thereto, the second signal input to the Y-th through-electrode is transmitted to an (X+1)-th through-electrode group.

A radio frequency switch has an antenna end, a first signal end for transmitting a first radio frequency signal, a second signal end for transmitting a second radio frequency signal, a third signal end for transmitting a third radio frequency signal, a first series path having a first switch, a second series path having a second switch, a third series path having a third switch, a first shunt path coupled between the first signal end and a node, a second shunt path coupled between the second signal end and the node, a common path coupled between the node and a first reference voltage end, and a third shunt path coupled between the third signal end and a second reference voltage end. The first series path and the second series path are connected to a common ground pad via the common path.

A device includes a voltage regulator circuit configured to pull up a voltage at an output terminal to equal to half of a supply voltage; multiple first transistors coupled between the output terminal and a voltage terminal providing the supply voltage; and a control circuit configured to pull down gate voltages of the first transistors from the supply voltage to a voltage level between the supply voltage and a ground voltage at a first time. The first transistors are configured to pull up the voltage at the output terminal to the supply voltage at a second time.

A radio frequency (RF) multiplexer circuit is provided. The multiplexer includes a first circuit coupled between a first input terminal and a first output terminal. The first circuit is configured and arranged to transfer a first RF signal coupled at the first input terminal to the first output terminal as a first output signal when a first control signal is at a first logic value. The multiplexer includes a second circuit coupled between a second input terminal and the first output terminal. The second circuit is configured and arranged to transfer a second RF signal coupled at the second input terminal to the first output terminal as a second output signal having a gain higher than the gain of the second RF signal when the first control signal is at a second logic value.

In some embodiments, a switching circuit can include a first node and a second node, and a plurality of transistors implemented in a stack configuration between the first node and the second node, with each transistor having a source, a drain and a gate, and the transistors being configured to be in an ON state or an OFF state to respectively allow or inhibit passage of a signal between the first and second nodes. The switching circuit can further include a bias circuit configured to bias the transistors from a bias node. The bias circuit can include a gate-gate resistor that couples each pair of neighboring transistors of the plurality of transistors, and a feed node coupled to the bias node, with the feed node being connected directly to the gate of a selected transistor of the plurality of transistors.

A radio frequency (RF) multiplexer circuit is provided. The multiplexer includes a first circuit coupled between a first input terminal and a first output terminal. The first circuit is configured and arranged to transfer a first RF signal coupled at the first input terminal to the first output terminal as a first output signal when a first control signal is at a first logic value. The multiplexer includes a second circuit coupled between a second input terminal and the first output terminal. The second circuit is configured and arranged to transfer a second RF signal coupled at the second input terminal to the first output terminal as a second output signal having a gain higher than the gain of the second RF signal when the first control signal is at a second logic value.

A logic two-to-one multiplexer includes: two input terminals; one output terminal; a control terminal. Four series-connected two-to-one multiplexers are connected such that a first multiplexer has its inputs connected to the input terminals, a last multiplexer has its output connected to the output terminal, and the other multiplexers have their respective inputs interconnected to the output of the previous multiplexer in the series association. Half of the multiplexers are controlled in reverse with respect to the other half of the multiplexers.

There is provided a power supply switching circuit including a first control signal output unit that outputs a signal exceeding a predetermined potential using a main power supply as a first control signal when a power supply voltage of the main power supply exceeds a predetermined reference voltage, a second control signal output unit that outputs the signal exceeding the predetermined potential using a standby power supply from a battery as a second control signal when a potential of the first control signal does not exceed the predetermined potential, and a power supply output unit that outputs the main power supply when the first control signal exceeds the predetermined potential and outputs the standby power supply when the second control signal exceeds the predetermined potential.

Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.

A fault diagnosis system is disclosed, including: a control unit, a first management board, a first pull-up unit, a second pull-up unit, a first pull-up switch, a second pull-up switch, and at least one central processing unit, the control unit is configured to receive physical partitioning information sent by the first management board, the first pull-up unit and the second pull-up unit are configured to pull up a fault indication signal of a fault diagnosis path to obtain a target signal, the first management board is configured to detect whether a level of the target signal is lower than a diagnosis threshold, and when the level of the target signal is lower than the diagnosis threshold, determine that a faulty central processing unit exists in the at least one central processing unit.