An amplifier system may include a first stage having a plurality of inputs configured to receive a differential pulse-width modulation input signal and generate an intermediate signal based on the differential pulse-width modulation input signal, a quantizer configured to generate a modulated signal based on the intermediate signal, a single-ended class-D output stage configured to generate a single-ended output signal as a function of the differential pulse-width modulation input signal, a feedback network configured to feed back the single-ended output signal to a first input of the plurality of inputs and to feed back a ground voltage to a second input of the plurality of inputs, a plurality of buffers, each particular buffer configured to receive a respective component of the differential pulse-width modulation input signal and generate a respective buffered component, and an input network coupled between the plurality of buffers and the first stage. Each particular buffer of the plurality of buffers may include a buffering subcircuit configured to buffer the respective component of the differential pulse-width modulation input signal associated with the particular buffer in order to generate the respective buffered component and a biasing subcircuit configured to limit a magnitude of the respective component of the differential pulse-width modulation input signal driven to circuitry of the buffering subcircuit for driving the respective buffered component.

A bootstrapped switch includes a first transistor, a second transistor, a first capacitor, three switches, and a switch circuit. The switch circuit includes a first switch, a second switch, a second capacitor, and a resistor. The first transistor receives the input voltage and outputs the output voltage. The first terminal of the second transistor receives the input voltage, and the second terminal of the second transistor is coupled to the first terminal of the first capacitor. The control terminal of the first switch receives a clock. The second switch is coupled between the control terminal of the first transistor and the first switch. The second capacitor is coupled between the control terminal of the first switch and the control terminal of the second switch. The resistor is coupled between the control terminal of the second switch and a reference voltage.

A bootstrapped switch includes a first transistor, a second transistor, a first capacitor, three switches, and a switch circuit. The switch circuit includes a first switch, a second switch, a second capacitor, and an inverter circuit. The first transistor receives the input voltage and outputs the output voltage. The first terminal of the second transistor receives the input voltage, and the second terminal of the second transistor is coupled to the first terminal of the first capacitor. The control terminal of the first switch receives a clock. The second switch is coupled between the control terminal of the first transistor and the first switch. The input terminal of the inverter circuit is coupled to the control terminal of the first switch. The second capacitor is coupled between the control terminal of the first transistor and the output terminal of the inverter circuit.

A drive device drives a motor serving as a load. A first upstream switch is disposed upstream from the motor and a first downstream switch is disposed downstream from the motor in a first current path of current flowing via the motor. A second upstream switch is disposed upstream from the motor and a second downstream switch is disposed downstream from the motor in a second current path of current flowing via the motor. A direction of the current flowing in the motor when current flows in the first current path is different from a direction of the current flowing in the motor when current flows in the second current path. The first upstream drive circuit stops flow of current via the first upstream switch when the current flowing through the first upstream switch becomes greater than or equal to a current threshold.

A gate drive circuit that drives a power device by controlling charge and discharge of gate capacitance of the power device includes: a first semiconductor switch that charges the gate capacitance by being brought into conduction according to a first control signal; a second semiconductor switch that discharges the gate capacitance by being brought into conduction according to a second control signal; and a slew rate control circuit that is connected between a gate of the power device and a ground line, and controls a slew rate during discharge. The slew rate control circuit includes a capacitor and a third semiconductor switch connected in series. The third semiconductor switch is brought into conduction according to the second control signal.

A radio frequency (RF) switching circuit is provided. The RF switching circuit includes a low-figure-of-merit (FOM) switching path that requires a longer duration to be switched on and off and a high-FOM switching path having a higher FOM than the low-FOM switching path but that can be switched on and off faster than the low-FOM switching path. In one aspect, the RF switching circuit passes an RF signal via the high-FOM switching path while toggling the low-FOM switching path to help reduce overall switching time of the RF switching circuit. In another aspect, the RF switching circuit passes the RF signal via the low-FOM switching path whenever the low-FOM switching path is switched on to help improve overall FOM of the RF switching circuit. As a result, the RF switching circuit may achieve a good overall response time and a reasonable overall FOM.

According to one aspect of embodiments, a drive circuit of a normally-ON transistor includes: a normally-OFF transistor that includes a main current path connected in serial to a main current path of the normally-ON transistor; and a buffer circuit that supplies, to a gate of the normally-ON transistor, a control signal for controlling turning ON and OFF of the normally-ON transistor, whose high-voltage side and low-voltage side are biased by a bias voltage supplied from a power source unit.

An electric circuitry for signal transmission comprises a transmission gate having an input node to apply an input signal. The transmission gate includes a first transistor having an electric conductive channel of a first type of conductivity and a second transistor having an electric conductive channel of a second type of conductivity. The electric circuitry comprises a control circuit to control the signal transmission of the transmission gate. The control circuit is configured to generate a first and second control signal to control the conductivity of the first and second transistor in dependence on a voltage level of the input signal.

A solid-state relay includes a semiconductor switch and a voltage boost block. The semiconductor switch has a control input, which causes the semiconductor switch to shift from an open, non-conducting position to a closed, conducting position when a voltage is applied to the control input. The voltage boost block includes a boost converter and a ground connector. A voltage output of the semiconductor switch is electrically connected to a voltage input of the boost converter. A voltage output of the boost converter is electrically connected to the control input. The ground connector of the boost converter is electrically connected to a voltage input of the semiconductor switch When the semiconductor switch is in the closed position, the semiconductor switch is maintained in a closed position in the absence of another control signal.

Provided is a switching circuit including an input terminal, a switching terminal, a ground terminal, a bootstrap terminal, a high side transistor connected to the input terminal and the switching terminal, a low side transistor connected to the switching terminal and the ground terminal, a bootstrap capacitor connected to the switching terminal and the bootstrap terminal, a bootstrap switch including a PMOS transistor, and a driver circuit that turns on the bootstrap switch in a period in which the low side transistor is on and that turns off the bootstrap switch in a period in which the low side transistor is off, in which the driver circuit includes a level shifter and a buffer, and the level shifter includes an output line, a first resistance, a first transistor, a second resistance, a third resistance, a second transistor, a third transistor, a first capacitor, and a fourth transistor.