A switch device includes an output transistor, an overcurrent protection circuit configured to be capable of performing an overcurrent protection operation in which magnitude of target current flowing in the output transistor is limited to a predetermined upper limit current value or less, and a control circuit configured to be capable of controlling a state of the output transistor and capable of changing the upper limit current value among a plurality of current values including a predetermined first current value and a predetermined second current value less than the first current value. The control circuit can limit the magnitude of the target current to the first current value or less in response to the magnitude of the target current reaching the first current value, and then change the upper limit current value to the second current value.

A system includes an output terminal and a linear switch circuit coupled to the output terminal. The linear switch circuit includes a first power field-effect transistor (FET) having: a first channel width; a control terminal; a first current terminal; and a second current terminal, wherein the second current terminal is coupled to the output terminal. The linear switch circuit also includes a second power FET having: a second channel width smaller than the first channel width; a control terminal; a first current terminal coupled to the first current terminal of the first power FET; and a second current terminal coupled to the output terminal. The system also comprises a control circuit coupled to the control terminal of the first power FET and to the control terminal of the second power FET. The control circuit detects a drain-to-source voltage (V.sub.DS) saturation condition and controls the first and second power FETs accordingly.

A semiconductor device, including a control circuit that has a gate control circuit driving a power semiconductor element. The control circuit further includes a plurality of alarm detection circuits respectively detecting a plurality of abnormalities, a protection circuit stopping the gate control circuit responsive to the detection of any abnormality, an alarm signal generation circuit generating an alarm signal responsive to the detected abnormality, a warning detection circuit detecting a warning before any of the abnormalities is detected, and a pulse generation circuit generating a warning signal while the warning is being detected. The alarm signal is a one-shot pulse having a pulse width thereof corresponding to the detected abnormality, such that alarm signals generated responsive to different abnormalities have different pulse widths. The warning signal includes a plurality of successive pulses, each of which has a pulse width smaller than any of the pulse widths of the alarm signals.

A semiconductor element drive device is provided to solve a problem that because a case of a change in the temperature of the semiconductor element or a current flowing through the semiconductor element is not take into consideration, switching loss and noise cannot be reduced sufficiently. In accordance with input sensing information (temperature T, current I), a timing control unit 3 outputs a delay signal Q to control timing of driving a current increasing circuit 5 so that a reduction of switching loss of an IGBT 101 is maximized. When the IGBT 101 is in turn-on mode or turn-off mode, the current increasing circuit 5 outputs a drive signal in response to the delay signal Q delayed by a given time from output of the drive instruction signal P. In this way, the current increasing circuit 5 increases the current that causes the gate capacitor of the IGBT 101 to be charged/discharged in response to the delay signal Q, thereby increasing a switching speed to reduce switching loss.

Solid state switching device including: a pair of line terminals including first and second line terminals for electrical connection with a corresponding phase conductor of an electric line; a switching assembly including one or more solid state power switches, the switching assembly having a first and second power terminals electrically connected with the first and second lines terminals, respectively; a heat sink element in thermal coupling with the switching assembly to adsorb heat from the switching assembly; an additional heat extraction arrangement to extract heat from the switching assembly and convey at least a portion of the adsorbed heat along the phase conductor through the first and second line terminals.

Provided is a driver circuit that controls an output unit that switches whether or not to supply a current to an output line, in accordance with a potential difference between a first control signal to be input and a voltage of the output line. The driver circuit comprises a control line that transmits the first control signal to the output unit; a low potential line to which a predetermined reference potential is applied; a first connection switching unit that switches whether or not to connect the control line and the low potential line, in accordance with a second control signal; and a cutoff unit that is provided in series with the first connection switching unit between the control line and the low potential line and cuts off the control line and the low potential line based on a potential of the low potential line.

A driver circuit includes a high side transistor, a low side transistor, a first trigger circuit, and a second trigger circuit. The high side transistor has a first control terminal and a first current path coupled between a first voltage terminal and an output voltage terminal. The low side transistor has a second control terminal and a second current path coupled between the output voltage terminal and ground. The first trigger circuit is coupled to the first control terminal, the first voltage terminal, and the output voltage terminal. The first trigger circuit is operable to protect the high side transistor. The second trigger circuit is coupled to the second control terminal, the first trigger circuit, and ground. The second trigger circuit is operable to protect the low side transistor.

In a power feeding control device, N-channel first FET and second FET are located in a current path for current flowing from a positive terminal to a negative terminal. The drain of the first FET is located downstream of the source. The drain of the second FET is located upstream of the source. The cathode of a first diode is connected to the negative terminal. A first drive circuit and a second drive circuit switch ON or OFF the first FET and the second FET by adjusting the gates of the first FET and the second FET, with respect to the cathode of the first diode.

A semiconductor device including a plurality of power modules each of which includes a power semiconductor switching element that has a temperature detection diode, and a drive circuit that has an output circuit for switching on and off the power semiconductor switching element, and that outputs a warning signal for calling attention if the value of the forward voltage of the temperature detection diode becomes equal to or smaller than a first reference voltage value, and that outputs a protection operation signal for stopping the on/off operation of the power semiconductor switching element if the value of the forward voltage becomes equal to or smaller than a second reference voltage value smaller than the first reference voltage value. The semiconductor device outputs the logical sum of the warning signals of the individual power modules as an external warning signal.

A resistance device (100) includes a field-effect transistor (TN) and a voltage applying circuit (1). The voltage applying circuit (1) applies a control voltage (Vgs) between the gate and source of the field-effect transistor (TN) according to a temperature (T) to control a resistance value (R) between the drain and source of the field-effect transistor (TN). The control voltage (Vgs) is a voltage obtained by adding a correction voltage (Vc) to a reference voltage (Vgs0). The correction voltage (Vc) depends on the temperature (T) and is set to be zero at a first temperature (T1).