A system, a switch assembly and an associated method. The system includes a number of switch assemblies, each including a switch module, isolation circuits, a detection unit, and a drive unit. The switch module includes power switch devices connected in parallel. The switch modules are connected in series. The isolation circuits each are connected in series to a gate terminal of at least one corresponding power switch device of the power switch devices. Each isolation circuit includes a capacitor or a controllable switch. The detection unit detects faults in at least one of the power switch devices. The drive unit is coupled to the switch module via the isolation circuits for driving the power switch devices of the corresponding switch module, and when the fault is detected, the drive unit is for turning on the power switch devices parallel connected to the at least one of faulty power switch devices.

A silicon controlled rectifier (SCR) circuit is configured to shunt electrostatic discharge (ESD) current from a node to a reference voltage. The SCR circuit includes a first bipolar PNP transistor having a first emitter connected to the node, a first base, and a first collector. A second bipolar NPN transistor has a second collector sharing a first region with the first base, a second base sharing a second region with the first collector, and an emitter electrically connected to the reference voltage. A guard region is configured and arranged to delay triggering of the SCR circuit in response to an ESD event by impeding current flow in the second region.

A control circuit for an electronic switch includes a first power switch receiving a common input signal and a first voltage input and a second power switch receiving the common input signal and a second voltage input. The first and second power switches switchably connect the first voltage input and the second voltage input, respectively, to a common output in response to the common input signal. The second voltage input is opposite in polarity to the first voltage input, and the first power switch and the second power switch are configured to asynchronously connect the first voltage input and the second voltage input, respectively, to the common output in response to the common input signal, the electronic switch being switched according to the first voltage input or the second voltage input being connected to the common output.

A semiconductor device includes a plurality of first transistor cells and a plurality of second transistor cells that are electrically connected in parallel between a collector electrode and an emitter electrode. A gate voltage on each of the plurality of first transistor cells is controlled by a first gate interconnection. A gate voltage on each of the plurality of second transistor cells is controlled by a second gate interconnection. A drive circuit is configured to: apply an ON-voltage of the semiconductor device to each of the first and second gate interconnections when the semiconductor device is turned on; and after a lapse of a predetermined time period since start of application of the ON-voltage, apply an OFF-voltage of the semiconductor device to the second gate interconnection and apply an ON-voltage to the first gate interconnection.

A switch for controlling a power supply and a method of operating the switch are disclosed. The switch includes a first transistor having a drain and a source connected between V.sub.IN and V.sub.OUT and a gate connected to be driven to a first voltage that is greater than V.sub.IN, an external capacitor operable, when connected to the gate of the first transistor, to control a rise time of V.sub.OUT, and a circuit coupled to the gate of the first transistor and to the external capacitor, the circuit connected to couple the external capacitor to the gate of the first transistor responsive to an enable signal turning on and to uncouple the external capacitor from the gate of the first transistor responsive to the voltage on the gate reaching the first voltage.

An electronic circuit includes a gate driver circuit. The gate driver circuit receives an input signal and a signal corresponding to a current through a switch, and produces, using the input signal, an output signal for controlling the switch. In response to the input signal being de-asserted, the gate driver circuit may turn the switch off at a normal turn-off rate when the current through the switch is less than an overcurrent (OC) threshold, and at an OC turn-off rate that is slower than the normal turn-off rate when the current through the switch is greater than the OC threshold.

Provided is an overcurrent protection circuit including an overcurrent detection unit configured to compare an output current flowing through a switch element and a predetermined overcurrent detection value to generate an overcurrent detection signal, an output activation detection unit configured to compare an output voltage and a predetermined threshold voltage to generate an output activation detection signal, a logic unit configured to combine the overcurrent detection signal and the output activation detection signal to generate a logic operation signal, and a diagnostic output unit configured to provide diagnostic output, the logic unit shifting the logic operation signal to a logic level of abnormal state when the overcurrent detection signal is shifted to a logic level of overcurrent detection state and holding the logic operation signal at that logic level, unless the output activation detection signal is shifted to a logic level of output activation state.

A circuit for reducing collector-emitter voltage (V.sub.CE) overshoot in an insulated gate bipolar transistor (IGBT) is provided. The circuit includes circuitry operable to generate a pulse which has a rising edge synchronized to the moment when collector or emitter current of the IGBT begins to fall during turn-off of the IGBT and a width which is a fraction of a duration of the V.sub.CE overshoot. The circuitry is further operable to combine the pulse with a control signal applied to a gate of the IGBT so as to momentarily raise the gate voltage of the IGBT during turn-off of the IGBT to above a threshold voltage of the IGBT for the duration of the pulse. A corresponding method of reducing V.sub.CE overshoot in an IGBT also is provided.

Systems, circuits, and methods for operating an Insulated-Gate Bipolar Transistor (IGBT) are provided. A circuit is to include a first driver for the IGBT, the first driver having a first resistance and being connectable to the gate of the IGBT. The circuit is further described to include a second driver for the IGBT, the second driver having a second resistance different from the first resistance and also being connectable to the gate of the IGBT. The circuit is also described to include a controller that receives at least two inputs regarding operating characteristics of the IGBT and based on the at least two inputs decides whether to connect the first or second driver to the gate of the IGBT during power-down of the IGBT.

Disclosed examples include integrated circuits, output driver circuits and protection circuits to protect an output transistor connected between a driver output node and a first intermediate node, including a resistor connected between the output node and a gate terminal of the output transistor, a diode connected between a second intermediate node and the output transistor gate terminal, and a switching device to electrically couple the second intermediate node with a reference node to turn on the output transistor to allow a second transistor to control a voltage of the output node when a control signal is in a first state, and to disconnect the second intermediate node from the reference node to prevent current flow through the resistor to control a gate voltage of the output transistor when the control signal is in a different second state.