In a power feeding control device, N-channel first FET and second FET are located in a current path for current flowing from a positive terminal to a negative terminal. The drain of the first FET is located downstream of the source. The drain of the second FET is located upstream of the source. The cathode of a first diode is connected to the negative terminal. A first drive circuit and a second drive circuit switch ON or OFF the first FET and the second FET by adjusting the gates of the first FET and the second FET, with respect to the cathode of the first diode.

A switch circuit of an embodiment includes a radio-frequency switch and a level shifter circuit. The radio-frequency switch, which includes a first switch group and a second switch group each including a plurality of switches, switches transmission/reception of a radio-frequency signal. The level shifter circuit outputs a first signal for controlling ON/OFF of each switch of the first switch group and a second signal for controlling ON/OFF of each switch of the second switch group.

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.

A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its V.sub.GS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero V.sub.GS type, or a mix of positive-logic and zero V.sub.GS type FETs with end-cap FETs of the zero V.sub.GS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

The switch device includes a first circuit. The first circuit has a first end coupled between a first terminal and a second terminal, and the first circuit has the second end coupled between the first terminal and the second terminal or coupled to a third terminal. The first circuit includes a first switch and a second switch. The first switch is coupled between the first end and the second end of the first circuit and is turned on or off according to a first control signal. The second switch is connected to the first switch in parallel and is turned on or off according to a second control signal. The first switch and the second switch include transistors of the same type. In a surge protection mode, the second switch is turned on to dissipate the surge current.

Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

Embodiments are directed to rectifiers using a single bias current or bias current path to bias multiple rectifying elements. A rectifier that has multiple rectifier stages coupled together serially includes a bias current path coupled to each of the rectifier stages. The bias current path is configured to simultaneously bias rectifying elements in each of the rectifier stages by using a bias current to bias a first rectifying element and reusing the bias current to bias other rectifying elements.

A radio frequency (RF) switching circuit is provided. The RF switching circuit includes a low-figure-of-merit (FOM) switching path that requires a longer duration to be switched on and off and a high-FOM switching path having a higher FOM than the low-FOM switching path but that can be switched on and off faster than the low-FOM switching path. In one aspect, the RF switching circuit passes an RF signal via the high-FOM switching path while toggling the low-FOM switching path to help reduce overall switching time of the RF switching circuit. In another aspect, the RF switching circuit passes the RF signal via the low-FOM switching path whenever the low-FOM switching path is switched on to help improve overall FOM of the RF switching circuit. As a result, the RF switching circuit may achieve a good overall response time and a reasonable overall FOM.

First and second switches are connected in series between first and second terminals. A third switch is provided between a first node between the first terminal and the first switch, and a first resistive-element. A fourth switch is provided between a second node between the first and second switches, and the reference power-source. A controller switches the first to fourth switches between conduction and non-conduction states. First, third, fifth, and seventh delay-circuits are provided between the first to fourth switches and the controller and delay first, second, third, fourth control signals for switching the first to fourth switches from a conduction state to a non-conduction state, respectively. Second, fourth, sixth, and eighth delay-circuits are provided between the first to fourth switches and the controller and delay the first, second, third, fourth control signals for switching the first to fourth switches to a non-conduction state to a conduction state, respectively.

Methods and apparatuses for use in tuning reactance are described. Open loop and closed loop control for tuning of reactances are also described. Tunable inductors and/or tunable capacitors may be used in filters, resonant circuits, matching networks, and phase shifters. Ability to control inductance and/or capacitance in a circuit leads to flexibility in operation of the circuit, since the circuit may be tuned to operate under a range of different operating frequencies.