A power switch device includes a first terminal intended to be connected to a source of a first supply potential, a second terminal configured to supply a second potential, and a third terminal intended to be connected to a second source of a third supply potential. The device includes a first PMOS transistor having a source connected to the second terminal and a drain connected to the third terminal, a second PMOS transistor having a source connected to the second terminal, and a third PMOS transistor having a source connected to the first terminal and a drain connected to the drain of the second transistor. A control circuit generates gate control signals to control operation of the first, second and third PMOS transistors dependent on the first, second, and third supply potentials.

A method for the delivery of power to subthreshold (sub-Vt) circuits uses unused current during idle-mode operation of super-threshold (super-Vt) circuits is used to supply sub-Vt circuits. Algorithmic and circuit techniques use dynamic management of idle cores when reusing the leakage current of the idle cores. A scheduling algorithm, longest idle time-leakage reuse (LIT-LR) enables energy efficient reuse of leakage current, which generates a supply voltage of 340 mV with less than ±3% variation across the tt, ff, and ss process corners. The LIT-LR algorithm reduces the energy consumption of the switch and the peak power consumption by, respectively, 25% and 7.4% as compared to random assignment of idle cores for leakage reuse. Second, a usage ranking based algorithm, longest idle time-simultaneous leakage reuse and power gating (LIT-LRPG) enables simultaneous implementation of power gating (PG) and leakage reuse in a multiprocessor system-on-chip (MPSoC) platform.

Described herein are switches with asymmetrical anti-series varactor pairs to improve switching performance. The disclosed switches can include asymmetrical varactor pairs to reduce distortions. The asymmetry in the varactor pairs can be associated with geometry of each varactor in the pair. The disclosed switches can stack both symmetrical and asymmetrical varactor pairs. The disclosed switches with asymmetrical anti-series varactor pairs can be configured to improve both H2 and H3 simultaneously.

A voltage tracking circuit is provided and includes first and second P-type transistors and a voltage reducing circuit. The drain of the first P-type transistor is coupled to a first voltage terminal. The voltage reducing circuit is coupled between the first voltage terminal and the gate of the first P-type transistor. The voltage reducing circuit reduces a first voltage at the first voltage terminal by a modulation voltage to generate a control voltage and provides the control voltage to the gate of the first P-type transistor. The gate of the second P-type transistor is coupled to the first voltage terminal, and the drain thereof is coupled to a second voltage terminal. The source of the first P-type transistor and the source of the second P-type transistor are coupled to the output terminal of the voltage tracking circuit. The output voltage is generated at the output terminal.

A die-to-die data transmitter is disclosed with a pull-up one-shot circuit and a pull-down one-shot circuit, each forming a delay circuit that determines a variable preemphasis period.

Described are apparatus and methods for control of multi-channel load switches with synchronized power up/down timing sequences. The slew rate control methods of the PMOS load switches contained in the N Multi-channel configuration is also described. A preferred slew rate control circuit includes a power PMOS transistor that is capable of handling load currents of several amperes along with an integrated controller. The integrated controller allows the user to program the power on/off sequences of each of the load switch channels by simply using a single or multiple input enable input pins.

Apparatus and circuits with dual threshold voltage transistors and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a first layer comprising a first III-V semiconductor material formed over the substrate; a first transistor formed over the first layer, and a second transistor formed over the first layer. The first transistor comprises a first gate structure comprising a first material, a first source region and a first drain region. The second transistor comprises a second gate structure comprising a second material, a second source region and a second drain region. The first material is different from the second material.

Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

A bi-directional voltage converter of a smart card includes switching elements connected between an input node and an output node and a start-up transistors whose channel width over channel length is smaller than a channel width over channel length of the switching element. The bi-directional voltage converter stores a driving voltage applied to an output node in a storage capacitor during a booting operation and provides the voltage stored in the storage capacitor to an input node. The bi-directional voltage converter may boost another driving voltage at the input node step-wisely and may perform bi-directional voltage converting with reduced occupied area and high efficiency.

A drive device driving a power converter that includes a switching element formed from a wide bandgap semiconductor, includes a PWM-signal output unit that generates a drive signal that drives the switching element with PWM; an on-speed reducing unit that, when the switching element is changed from off to on, reduces a change rate of the drive signal; and an off-speed improving unit that, when the switching element is changed from on to off, draws charge from the switching element at a high speed and with a charge drawing performance higher than that at a time when the switching element is changed from off to on.