A power switching circuit includes a first switch circuit, a second switch circuit, a control circuit, and a driver circuit. The first switch circuit receives a first power voltage and coupled to an output terminal. The first switch circuit includes a first P-type transistor and a second P-type transistor coupled in series. The second switch circuit receives a second power voltage and coupled to the output terminal. The second switch circuit includes a third P-type transistor and a fourth P-type transistor coupled in series. The control circuit generates a control signal according to an output voltage at the output terminal, a power state signal, and one of the first power voltage and the second power voltage. The driver circuit generates a first driving signal or a second driving signal according to the control signal to control the first switch circuit or the second switch circuit.

A plurality of switching units are provided, and a controller performs control in an antiphase manner to approximately synchronize a rise of a control signal applied to one of the switching units with a fall of a control signal for switching applied to any one of the other switching units and synchronize a fall of the control signal applied to the one of the switching units with a rise of the control signal for switching applied to the any one of the other switching units. When control in an antiphase manner is disabled, control is performed to prevent rises or falls from coinciding with each other between the switching units. Output signals from the switching units are input to rectifiers and are combined by a combiner to become an output signal.

A cell logic structure for a battery-indifferent or pure energy harvesting multi-mode system, a battery-indifferent or pure energy harvesting multi-mode system, a method of operating a cell logic structure for a battery-indifferent or pure energy harvesting multi-mode system, and a method of operating battery-indifferent or pure energy harvesting multi-mode system. The cell gate structure comprises a CMOS gate circuit; a header circuit coupled to the CMOS gate circuit and comprising first and second header transistors for coupling in parallel between a supply voltage and the CMOS gate circuit; and a footer circuit coupled to the CMOS gate circuit and comprising first and second footer transistors for coupling in parallel between the CMOS gate circuit and a ground voltage; wherein the header and footer circuits are configured for switching between different operation modes of the multi-mode system, the different operation modes chosen from a range from a normal mode in which feedback paths from an output of the CMOS gate circuit to the gate of the second header transistor and to the gate of the second footer transistor are substantially or fully disabled for full swing in the output voltage of the CMOS gate circuit, and a leakage suppression mode in which the feedback paths are substantially or fully enabled.

An apparatus including a main transistor-based switch having a first end node and a second end node and an ON-state linearization network that is coupled between the first end node and the second end node of the main transistor-based switch is disclosed. The ON-state linearization network is configured to receive a monitored signal that corresponds to a signal across the first end node and the second end node and cancel at least a portion of non-linear distortion generated by the main transistor-based switch when the main transistor-based switch is in an ON-state based on the monitored signal. A control signal applied to a control input of the ON-state linearization network causes the ON-state linearization network to activate when the main transistor-based switch is in the ON-state and to deactivate the ON-state linearization network when the main transistor-based switch is an OFF-state.

Described are apparatus and methods for a load switch with reset and deep sleep capability. The slew rate control methods of the PMOS load switches contained in the load switch configuration is also described. A preferred slew rate control circuit includes a power PMOS transistor that is capable of handling load currents of several amperes along with an integrated controller. The integrated reset and deep sleep functions allow the user to control the basic timing control of the voltages that are required by the system and to save battery power in an extended deep sleep mode such as storage and shipping.

A technique of operating a device comprising a patterned conductor layer defining source electrode circuitry and drain electrode circuitry for a plurality of transistors; a semiconductor layer providing a respective semiconductor channel for each transistor between source electrode circuitry and drain electrode circuitry; and gate electrode circuitry overlapping the semiconductor channels of the plurality of transistor devices for switching the semiconductor channels between two or more levels of conductance; wherein the technique comprises using one or more further conductors independent of said gate electrode circuitry to capacitatively induce a reduction in conductivity of said one or more areas of said semiconductor layer outside of said semiconductor channels.

A transistor device may include an n-type transistor. The transistor device may further include a first bias voltage unit, which is electrically connected to the n-type transistor and configured to apply a first positive bias voltage to a drain terminal of the n-type transistor when the n-type transistor is in an off state. The transistor device may further include a second bias voltage unit electrically, which is connected to the n-type transistor and configured to apply a second positive bias voltage to a source terminal of the n-type transistor when the n-type transistor is in the off state.

An integrated circuit, including: at least three integrated circuit portions mutually spaced on a single electrically insulating die, the integrated circuit portions being mutually galvanically isolated; and signal coupling structures on the die to allow communication of signals between the integrated circuit portions while maintaining the galvanic isolation therebetween.

Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

A leakage-current compensation circuit including: a first node for connection of a first component, a first leakage current flows through the first component and node with a given polarity, the magnitude of the first leakage current dependent on a first potential difference across the first component; a second component connected to a second node with a second leakage current flowing through the second component and node, the magnitude of the second leakage current dependent on a second potential difference across the second component; a current mirror connected to the first and second nodes to cause a compensation current, the magnitude of the compensation current dependent on the magnitude of the second leakage current; a differential amplifier connected in series with the second component along a current path carrying the second leakage current; and an AC coupling superimposing an AC-component of the first potential difference on the second potential difference.