It is an object of the present invention to provide a buffer circuit that reduces a reverse voltage applied to transistors being a complementary pair during turn-on and turn-off. A buffer circuit is a buffer circuit that turns on and turns off a switching element and includes a drive-side element that has an end connected to a base of a drive transistor and a sink-side element that has an end connected to a base of a sink transistor. The drive-side element and the sink-side element are respectively a drive-side diode and a sink-side diode, or a drive-side capacitor and a sink-side capacitor.

The switching power source device obtains a desired DC voltage by controlling the current flowing through a coil by turning on and off a switching element by a PWM control. In the PWM ON period to turn on the switching element by the PWM control, the switching power source device is enabled to switch the switching element by a first pulse signal whose cycle is shorter than the PWM cycle and whose pulse width is gradually increased, in a first period just after the start of the PWM ON period. Further, the switching power source device is enabled to switch the switching element by a PWM signal based on the PWM control after the first period in the PWM ON period has elapsed. According to this approach, it is possible to reduce the harmonic noise.

A vehicle powertrain includes an IGBT, having a Kelvin emitter and a mirror current sense, configured to energize an inductance, a first switch configured to draw a current from a gate of the IGBT at a rate based on a resistance engaged by the first switch while a current of the inductance exceeds a threshold, and a second switch configured to increase the rate in response to the current being less than the threshold. In one embodiment, the current is based on a filtered voltage across a resistor connected between the mirror current sense and chassis ground while the Kelvin emitter is connected to chassis ground. In another embodiment, the current is based on a filtered voltage across a resistor connected between the mirror current sense and the Kelvin emitter.

A DC switching device has at least one switching unit which is arranged between two terminals. Further, the DC switching device has a control unit for controlling the at least one switching unit. The switching unit has a first and a second semiconductor switching element, which are arranged in parallel with one another, the first switching element being a high-voltage switching element and the second switching element being a low-power-loss switching element. The switching unit is controllable by the control unit in such a way that, when the switching unit is switched off, initially the second switching element is switched to be non-conductive, and subsequently the first switching unit is switched to be non-conductive, and when the switching unit is switched on, initially the first switching element is switched to be conductive and subsequently the second switching element is switched to be conductive.

A gate drive device for a switching element includes: a surge voltage detection circuit for detecting a surge voltage when the switching element is turned off; a delay circuit for outputting a timing signal when a predetermined delay time elapses after a turn-off start signal is input; and a driving current output unit for starting to supply a first gate drive current to the switching element when the turn-off start signal is input, and for starting to supply a second gate drive current to the switching element when the delay circuit outputs the timing signal. The delay circuit is configured to change and set the delay time when the surge voltage is different from a target value.

A vehicle powertrain includes an electric machine, an inverter including an IGBT having a gate configured to flow current through a phase of the electric machine, and a gate driver. The gate driver is configured to supply power onto the gate via a voltage regulated source, and in response to a collector current of the IGBT exceeding a previous steady state current through the phase, transition to a current regulated source to drive the gate. The gate driver may be configured to delay the transition by a predetermined time that is based on a difference between the previous steady state current and a reverse recovery peak current.

The present disclosure provides a debounced solid state switching device comprised of at least two insulated-gate bipolar transistors (“IGBTs”) within a parallel architecture. Multiple pairs of IGBTs may be used in a parallel architecture to extend ampacity and improve voltage withstand capability. The device provides improved flexibility and portability to facilitate time and cost efficiency, as the size and complexity of the device is directly dependent on the needs of the user. Furthermore, the procurement of the components of the device is simple, providing greater accessibility.

An inverter for an electric vehicle comprises a phase leg having series-connected upper and lower transistors between a positive bus and a ground bus. Upper and lower gate drive circuits supply gate drive signals to the upper and lower transistors. Each gate drive circuit includes an active clamp for deactivating the upper and lower transistors. The transistors are comprised of semiconductor devices, each having respective gate, collector, and emitter terminals. Each pair of gate and emitter terminals is adapted to provide an enhanced common source inductance therebetween. Each gate terminal is adapted to be tied to a ground voltage of the drive circuits. Each respective active clamp is comprised of a p-channel MOSFET having a source terminal connected to the gate terminal of a respective transistor and having a drain terminal connected to the emitter terminal of the respective transistor bypassing the respective enhanced common source inductance.

Power switch driver for driving a control terminal of a power switch to drive a load, the power switch driver having a in negative feedback circuit to control current delivered to the control terminal, the negative feedback circuit comprising:—a current output circuit comprising at least one of a current source and a current sink, the current output circuit for providing a said current of a said control terminal and configured to receive an output current control signal to control magnitude of the current provided by the current output circuit;—a terminal voltage input circuit for receiving a voltage from a said control terminal and to output an indication of said voltage;—an amplifier coupled to amplify the terminal voltage indication to generate an amplifier output; and—a reference voltage input circuit for receiving a reference voltage, comprising at least one resistor, the reference voltage input circuit coupled to a charge supply input of the amplifier, wherein—the power switch driver is configured to generate the output current control signal dependent on the amplifier output, and—the power switch driver is configured to reduce the current provided by the current output circuit responsive to an increase in the voltage received by the terminal voltage input circuit.

A vehicle powertrain includes an IGBT and a gate driver. The IGBT is configured to energize an electric machine. The gate driver is configured to apply an off voltage less than a threshold voltage onto a gate of the IGBT while the IGBT is operating in a saturation mode, and in response to expiration of a delay from a transition from saturation to linear mode, apply a voltage pulse above the off voltage to reduce flyback from the electric machine. The gate driver may be configured to, in response to expiration of a delay from a transition from saturation to linear mode, apply a voltage pulse above the off voltage and below the threshold to reduce flyback from the electric machine.