A semiconductor device that retains a state of a data storage element during a power reduction mode including supply rails and voltages, and a storage latch and a retention latch both powered by retention supply voltage that remains energized during a power reduction mode. The storage latch and the retention latch are both coupled to a retention node that is toggled between first and second states before entering the power reduction mode. The toggling causes the storage latch to latch the state of the data storage element during the normal mode, and the retention node enables the storage element to hold the state during the power reduction mode. The retention latch includes a retention transistor and a retention inverter powered by the retention supply voltage. The retention inverter keeps the retention transistor turned on and the retention transistor holds the state of the retention node during the power reduction mode.

An apparatus that includes a single event latchup (SEL) recovery circuit, a microprocessor operatively connected with the SEL recovery circuit, and an output maintenance circuit that maintains a state of the microprocessor prior to a power cycle of the microprocessor. The apparatus is configured to detect a SEL event or other fault via a watchdog circuit, initiate a power cycle of the microprocessor, retain a latch state from the microprocessor, and determine whether the microprocessor was restarted due to an SEL event. Responsive to determining that the microprocessor has failed to restart due to a persistent fault, the apparatus determines whether a prepower cycle limit is reached within a predetermined span of time, and selectively provide power to a load based on the latch state and the power cycle limit determination.

An apparatus that includes a single event latchup (SEL) recovery circuit, a microprocessor operatively connected with the SEL recovery circuit, and an output maintenance circuit that maintains a state of the microprocessor prior to a power cycle of the microprocessor. The apparatus is configured to detect a SEL event or other fault via a watchdog circuit, initiate a power cycle of the microprocessor, retain a latch state from the microprocessor, and determine whether the microprocessor was restarted due to an SEL event. Responsive to determining that the microprocessor has failed to restart due to a persistent fault, the apparatus determines whether a prepower cycle limit is reached within a predetermined span of time, and selectively provide power to a load based on the latch state and the power cycle limit determination.

A method of powering up a circuit includes powering up a latch circuit in a known latch state by applying a first power supply voltage differential of a first voltage domain across power supply terminals of the latch circuit. A current diode inhibits current diode in a current path between a latch node of the latch circuit and a power supply terminal when the power supply voltage differential is below a threshold voltage during the powering up in which the inhibiting prevents the latch circuit from switching from the known latch state during the powering up.

A device for providing a reset signal to one or more sequential logic circuits in an electronic system responsive to a supply voltage condition includes a first voltage detector circuit to generate a first pulse after the supply voltage rises to a first threshold voltage level. The device further includes a second voltage detector circuit to generate a second pulse after the supply voltage falls below a second threshold voltage level. The device additionally includes a latch circuit to store a first value based on the first pulse after the supply voltage rises to the first threshold voltage level, disable the first voltage detector circuit after storing the first value, reset to store a second value based on the second pulse after the supply voltage falls below the second threshold voltage level, and to disable the second voltage detector circuit after the resetting.

A control apparatus comprises a microcontroller, an auxiliary circuit, a delay module and a logical circuit; the microcontroller is connected to a first input end of the logical circuit via the auxiliary circuit and connected to a second input end of the logical circuit via the delay module, and an output end of the logical circuit is connected to a device to be controlled; if the microcontroller is reset in a process of outputting the closing control signal, a delay disabling signal becomes invalid, the delay module is enabled to output the closing control signal within a preset delay time, wherein the delay time is greater than or equal to a reset time. A power supply system is also provided to avoid a risk that an automobile suddenly loses power due to unexpected reset of the microcontroller.

An image display apparatus is disclosed. The image display according to an embodiment of the present disclosure includes a signal processing device including a first logic circuit to process a first voltage range of a voltage level of the input signal, a second logic circuit to process a second voltage range of the voltage level of the input signal, higher than the first voltage range, and a protection control circuit including a protection switch and a protection controller for controlling the protection switch, wherein the protection switch is turned on based on the protection controller being turned off or powered down. Accordingly, a breakdown phenomenon can be reduced in case of power off or power down.

A semiconductor device that retains a state of a data storage element during a power reduction mode including supply rails and voltages, and a storage latch and a retention latch both powered by retention supply voltage that remains energized during a power reduction mode. The storage latch and the retention latch are both coupled to a retention node that is toggled between first and second states before entering the power reduction mode. The toggling causes the storage latch to latch the state of the data storage element during the normal mode, and the retention node enables the storage element to hold the state during the power reduction mode. The retention latch includes a retention transistor and a retention inverter powered by the retention supply voltage. The retention inverter keeps the retention transistor turned on and the retention transistor holds the state of the retention node during the power reduction mode.

A semiconductor device that retains a state of a data storage element during a power reduction mode including supply rails and voltages, and a storage latch and a retention latch both powered by retention supply voltage that remains energized during a power reduction mode. The storage latch and the retention latch are both coupled to a retention node that is toggled between first and second states before entering the power reduction mode. The toggling causes the storage latch to latch the state of the data storage element during the normal mode, and the retention node enables the storage element to hold the state during the power reduction mode. The retention latch includes a retention transistor and a retention inverter powered by the retention supply voltage. The retention inverter keeps the retention transistor turned on and the retention transistor holds the state of the retention node during the power reduction mode.

A device for providing a reset signal to one or more sequential logic circuits in an electronic system responsive to a supply voltage condition includes a first voltage detector circuit to generate a first pulse after the supply voltage rises to a first threshold voltage level. The device further includes a second voltage detector circuit to generate a second pulse after the supply voltage falls below a second threshold voltage level. The device additionally includes a latch circuit to store a first value based on the first pulse after the supply voltage rises to the first threshold voltage level, disable the first voltage detector circuit after storing the first value, reset to store a second value based on the second pulse after the supply voltage falls below the second threshold voltage level, and to disable the second voltage detector circuit after the resetting.