This application provides a gallium nitride component and a drive circuit thereof. The gallium nitride component includes: a substrate; a gallium nitride (GaN) buffer layer formed on the substrate; an aluminum gallium nitride (AlGaN) barrier layer formed on the GaN buffer layer; and a source, a drain, and a gate formed on the AlGaN barrier layer. The gate includes a P-doped gallium nitride (P—GaN) cap layer formed on the AlGaN barrier layer, and a first gate metal and a second gate metal formed on the P—GaN cap layer. A Schottky contact is formed between the first gate metal and the P—GaN cap layer, and an ohmic contact is formed between the second gate metal and the P—GaN cap layer. In the technical solution provided in this application, the gallium nitride component is a normally-off component, and is conducive to design of a drive circuit.

A driver circuit includes a first deglitcher circuit that delays a rising edge or a falling edge of an input signal according to a mode control signal and supplies a first output signal. A second deglitcher circuit receives the first output signal and delays either a rising edge or a falling edge of the first output signal by a second delay according to the mode control signal and supplies a second output signal. Logic gates combine the first and second output signals to supply gate control signals for output transistors to drive the driver circuit output. A sum of the first delay and the second delay determines the total deglitch time defining a pulse width of pulses that are suppressed by the driver circuit and the second delay determines a non-overlap time. The non-overlap time overlaps in time with the total deglitch time.

A gate drive circuit according to an embodiment includes: a voltage detector that detects a voltage between a first terminal and a second terminal of a switching device; a delay circuit that outputs, with a delay for a predetermined time, a detected value of the voltage obtained from the voltage detector; and a first off-mode drive circuit and a second off-mode drive circuit that apply a control signal to a control terminal of the switching device for turning off the switching device, wherein the first off-mode drive circuit turns off the switching device faster than the second off-mode drive circuit, and stops its operation to turns off the switching device when the delayed voltage value output from the delay circuit exceeds a predetermined threshold value.

A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in series, referred to as “stacked” transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements comprise resistors. In another embodiment, the charge injection control elements comprise transistors. A method for controlling charge injection in a switch circuit is disclosed whereby injected charge is generated at resistively-isolated nodes between series coupled switching transistors, and the injected charge is conveyed to at least one node of the switch circuit that is not resistively-isolated.

A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in series, referred to as “stacked” transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements comprise resistors. In another embodiment, the charge injection control elements comprise transistors. A method for controlling charge injection in a switch circuit is disclosed whereby injected charge is generated at resistively-isolated nodes between series coupled switching transistors, and the injected charge is conveyed to at least one node of the switch circuit that is not resistively-isolated.

A gate drive device drives a gate of each of two semiconductor switching elements constituting upper and lower arms of a half bridge circuit. The gate drive device detects a peak value of an element voltage that is a voltage of a main terminal of one of the two semiconductor switching elements, as one semiconductor switching element, or a change rate of the element voltage during a change period in which the element voltage changes. The gate drive device determines whether an energization to the one semiconductor switching element during the change period is a forward energization in which a current flows in a forward direction or a reverse energization in which the current flows in a reverse direction.

A gate drive device drives a gate of each of two semiconductor switching elements constituting upper and lower arms of a half bridge circuit. The gate drive device detects a peak value of an element voltage that is a voltage of a main terminal of one of the two semiconductor switching elements, as one semiconductor switching element, or a change rate of the element voltage during a change period in which the element voltage changes. The gate drive device determines whether an energization to the one semiconductor switching element during the change period is a forward energization in which a current flows in a forward direction or a reverse energization in which the current flows in a reverse direction.

A gate drive device drives a gate of a semiconductor switching element constituting an upper or lower arm of a half bridge circuit which supplies an output current, which is alternating current, to a load. The gate drive device detects a peak value of an element voltage which is a voltage of a main terminal of the semiconductor switching element or a change rate of the element voltage when the semiconductor switching element is switching. The gate drive device acquires a maximum value among a plurality of peak values or a plurality of change rates during a predetermined detection period including a period in which the semiconductor switching element performs switching multiple number of times.

A gate drive device drives a gate of a semiconductor switching element constituting an upper or lower arm of a half bridge circuit which supplies an output current, which is alternating current, to a load. The gate drive device detects a peak value of an element voltage which is a voltage of a main terminal of the semiconductor switching element or a change rate of the element voltage when the semiconductor switching element is switching. The gate drive device acquires a maximum value among a plurality of peak values or a plurality of change rates during a predetermined detection period including a period in which the semiconductor switching element performs switching multiple number of times.

A selection circuit architecture makes it possible to perform upward and/or downward transitions in sets of sequences of slow and fast phases so as at the same time to solve the problems of inductive switching noise and the problems of currents in the supply rails. This solution has multiple advantages linked to the ease of implementation and flexibility of configurations that are possible for adapting to the specific constraints when designing the circuit.