An integrated circuit, a control method, and a system are provided, to improve reliability of the integrated circuit. The integrated circuit mainly includes a power supply pin (P1), a configuration pin (P4, P5), a switchable pull-up resistor (KR1, KR2), and a control unit (2011). The integrated circuit can provide a control signal for a target chip (202) by using the configuration pin (P4, P5) of the integrated circuit. In the integrated circuit, a first end of the switchable pull-up resistor (KR1, KR2) is connected to the power supply pin (P1), a second end of the switchable pull-up resistor (KR1, KR2) is connected to the configuration pin (P4, P5), and a control end of the switchable pull-up resistor (KR1, KR2) is connected to the control unit (2011). The power supply pin (P1) can receive a power supply voltage of the integrated circuit.

An integrated circuit, a control method, and a system are provided, to improve reliability of the integrated circuit. The integrated circuit mainly includes a power supply pin (P1), a configuration pin (P4, P5), a switchable pull-up resistor (KR1, KR2), and a control unit (2011). The integrated circuit can provide a control signal for a target chip (202) by using the configuration pin (P4, P5) of the integrated circuit. In the integrated circuit, a first end of the switchable pull-up resistor (KR1, KR2) is connected to the power supply pin (P1), a second end of the switchable pull-up resistor (KR1, KR2) is connected to the configuration pin (P4, P5), and a control end of the switchable pull-up resistor (KR1, KR2) is connected to the control unit (2011). The power supply pin (P1) can receive a power supply voltage of the integrated circuit.

A control system includes a control unit. When turning a bidirectional switch element ON, the control unit controls the bidirectional switch element to cause a time lag between a first timing and a second timing. The first timing is a timing when a voltage equal to or higher than a threshold voltage is applied to one gate electrode selected from a first gate electrode and a second gate electrode. The one gate electrode is associated with one source electrode selected from a first source electrode and a second source electrode and having a lower potential than the other source electrode. The second timing is a timing when a voltage equal to or higher than a threshold voltage is applied to the other gate electrode associated with the other source electrode having a higher potential than the one source electrode.

A control system includes a control unit. When turning a bidirectional switch element ON, the control unit controls the bidirectional switch element to cause a time lag between a first timing and a second timing. The first timing is a timing when a voltage equal to or higher than a threshold voltage is applied to one gate electrode selected from a first gate electrode and a second gate electrode. The one gate electrode is associated with one source electrode selected from a first source electrode and a second source electrode and having a lower potential than the other source electrode. The second timing is a timing when a voltage equal to or higher than a threshold voltage is applied to the other gate electrode associated with the other source electrode having a higher potential than the one source electrode.

A nanosecond pulser is disclosed. In some embodiments, the nanosecond pulser may include one or more switch circuits including one or more solid state switches, a transformer, and an output. In some embodiments, the transformer may include a first transformer core, a first primary winding wound at least partially around a portion of the first transformer core, and a secondary winding wound at least partially around a portion of the first transformer core. In some embodiments, each of the one or more switch circuits are coupled with at least a portion of the first primary winding. In some embodiments, the output may be electrically coupled with the secondary winding and outputs electrical pulses having a peak voltage greater than about 1 kilovolt and a rise time of less than 150 nanoseconds or less than 50 nanoseconds.

A nanosecond pulser is disclosed. In some embodiments, the nanosecond pulser may include one or more switch circuits including one or more solid state switches, a transformer, and an output. In some embodiments, the transformer may include a first transformer core, a first primary winding wound at least partially around a portion of the first transformer core, and a secondary winding wound at least partially around a portion of the first transformer core. In some embodiments, each of the one or more switch circuits are coupled with at least a portion of the first primary winding. In some embodiments, the output may be electrically coupled with the secondary winding and outputs electrical pulses having a peak voltage greater than about 1 kilovolt and a rise time of less than 150 nanoseconds or less than 50 nanoseconds.

Embodiments relate to a circuit implementation for controlling a delay of a clock signal. The clock delay control circuit includes a sensing circuit and a phase interpolator controlled by the sensing circuit. The sensing circuit generates a first control signal that increases when a level of a supply voltage increases, and decreases when the level of the supply voltage decreases. Moreover, the sensing circuit generates a second control signal that decreases when the level of the supply voltage increases, and increases when the level of the supply voltage decreases. The phase interpolator includes multiple paths, each having a different propagation delay. The coupling between each path and the output node of the phase interpolator is controlled by the control signals generated by the sensing circuit.

A transmitter merges even and odd data streams to drive a serialized signal. Identical even and odd drivers take turns driving symbols from respective even and odd streams using respective pull-up transistors and pull-down transistors. Each transistor exhibits a significant source-gate capacitance that is charged when the transistor is turned onto drive the serialized signal. Charging one of these capacitances loads the power supply and thus introduces noise. Each even and odd driver includes a pre-driver that times the charging of a source-gate capacitance in the active driver to the discharge of a source-gate capacitance in the inactive driver. The discharge of the source-gate capacitance in the inactive driver counters the effect of charging the active driver, providing much of the power required by the active driver and thus reducing supply noise.

A transmitter merges even and odd data streams to drive a serialized signal. Identical even and odd drivers take turns driving symbols from respective even and odd streams using respective pull-up transistors and pull-down transistors. Each transistor exhibits a significant source-gate capacitance that is charged when the transistor is turned onto drive the serialized signal. Charging one of these capacitances loads the power supply and thus introduces noise. Each even and odd driver includes a pre-driver that times the charging of a source-gate capacitance in the active driver to the discharge of a source-gate capacitance in the inactive driver. The discharge of the source-gate capacitance in the inactive driver counters the effect of charging the active driver, providing much of the power required by the active driver and thus reducing supply noise.

Examples of the disclosure include a coupler comprising an input port, an output port, a coupled port, an isolated port, a main line coupled between the input port and the output port, a coupled line coupled between the coupled port and isolated port, and one or more elements switchably coupled between the coupled port and the isolated port, the one or more elements including at least one of an inductive, capacitive, or resistive element.