A drive circuit of a power semiconductor element comprises a gate drive voltage generator to generate, based on an ON/OFF drive timing signal input to an input terminal, a gate drive voltage to be applied to a gate electrode of a switching element having the gate electrode for controlling a main current that flows between a first main electrode and a second main electrode, wherein the gate drive voltage generator includes a gate current limiting circuit in which a current limiter to limit a current and a voltage limiter to limit the magnitude of a voltage applied to both ends of the current limiter are connected in parallel.

Embodiments of this application disclose a drive circuit of a power device and a drive system, to drive the power device by using a small quantity of components. The drive circuit of the power device includes: a drive signal generation circuit, configured to generate a drive signal; a resistor and a capacitor that are connected in series, coupled to the drive signal generation circuit and the power device, and configured to control turn-on and turn-off of the power device based on the drive signal; and a voltage clamp circuit, coupled to the power device, and configured to control a gate voltage of the power device to be not greater than a gate withstand voltage.

Provided is a semiconductor device capable of suppressing increase in size of a package and adjusting an amount of negative feedback. A power module as a semiconductor device includes an IGBT which is a switching element and a free wheel diode (FWD) parallelly connected to the switching element. The IGBT has, on a surface thereof, an emitter electrode and a gate electrode of the IGBT and a conductive pattern insulated from the emitter electrode and the gate electrode. The FWD has, on a surface thereof, an anode electrode of the FWD and a conductive pattern insulated from the anode electrode.

Provided is a semiconductor device capable of suppressing increase in size of a package and adjusting an amount of negative feedback. A power module as a semiconductor device includes an IGBT which is a switching element and a free wheel diode (FWD) parallelly connected to the switching element. The IGBT has, on a surface thereof, an emitter electrode and a gate electrode of the IGBT and a conductive pattern insulated from the emitter electrode and the gate electrode. The FWD has, on a surface thereof, an anode electrode of the FWD and a conductive pattern insulated from the anode electrode.

A current limiting circuit of a switching circuit, and a switching circuit are provided. The switching circuit uses a gallium nitride (GaN) power transistor as a main power transistor. The current limiting circuit includes a first terminal connected with a drain of the GaN power transistor, and a second terminal connected with a controller of the switching circuit. The current limiting circuit is configured to limit a current flowing out of a power supply terminal of the controller. The current limiting circuit suppresses a negative current flowing through the controller.

A current limiting circuit of a switching circuit, and a switching circuit are provided. The switching circuit uses a gallium nitride (GaN) power transistor as a main power transistor. The current limiting circuit includes a first terminal connected with a drain of the GaN power transistor, and a second terminal connected with a controller of the switching circuit. The current limiting circuit is configured to limit a current flowing out of a power supply terminal of the controller. The current limiting circuit suppresses a negative current flowing through the controller.

Techniques and apparatus for driving a transistor gate of a switched-mode power supply (SMPS) circuit. One example gate driver for a switching transistor of an SMPS circuit generally includes a first power supply rail; a reference rail; an output node for coupling to a control input of the switching transistor; a floating supply node; a pulldown transistor having a drain coupled to the output node of the gate driver and having a source coupled to the reference rail; and a pulldown logic buffer having a first power supply input coupled to the floating supply node, having a second power supply input coupled to the reference rail, and having an output coupled to a gate of the pulldown transistor. The floating supply node is configured to selectively receive power from the first power supply rail and the output node of the gate driver.

A number of monolithic multi-throw diode switch structures are described. The monolithic multi-throw diode switches can include a hybrid arrangement of diodes with different intrinsic regions, all formed over the same semiconductor substrate. In one example, two PIN diodes in a monolithic multi-throw diode switch have different intrinsic region thicknesses. The first PIN diode has a thinner intrinsic region, and the second PIN diode has a thicker intrinsic region. This configuration allows for both the thin intrinsic region PIN diode and the thick intrinsic region PIN diode to be individually optimized. As one example, for a switch functioning in a dedicated transmit/receive mode, the first transmit PIN diode can have a thicker intrinsic region than the second receive PIN diode to maximize power handling for the transmit arm and maximize receive sensitivity and insertion loss in the receive arm.

A number of monolithic multi-throw diode switch structures are described. The monolithic multi-throw diode switches can include a hybrid arrangement of diodes with different intrinsic regions, all formed over the same semiconductor substrate. In one example, two PIN diodes in a monolithic multi-throw diode switch have different intrinsic region thicknesses. The first PIN diode has a thinner intrinsic region, and the second PIN diode has a thicker intrinsic region. This configuration allows for both the thin intrinsic region PIN diode and the thick intrinsic region PIN diode to be individually optimized. As one example, for a switch functioning in a dedicated transmit/receive mode, the first transmit PIN diode can have a thicker intrinsic region than the second receive PIN diode to maximize power handling for the transmit arm and maximize receive sensitivity and insertion loss in the receive arm.

The invention relates to the field of power semiconductor devices. This invention discloses a drive circuit and device of a power switch. The input terminal of the drive circuit receives a pulse signal; the output terminal of the drive circuit is connected to a capacitor circuit. The capacitor circuit is used to provide a negative voltage for a first electrode of the power switch to turn off the power switch when the pulse signal is a turn-off signal; the drive circuit includes a capacitance adjustment unit. The capacitance adjustment unit includes a negative voltage adjustment element that can charge a capacitor whose voltage is lower than a predetermined voltage when the pulse signal is the turn-off signal.