A parameter calibration method is provided. The parameter calibration method includes: obtaining a control parameter to be calibrated; determining a simulation running error corresponding to a quantum chip; determining calibration data corresponding to the control parameter to be calibrated based on the simulation running error; and obtaining a calibrated control parameter by calibrating the control parameter to be calibrated based on the calibration data, wherein the calibrated control parameter is used for controlling operation of the quantum chip.

A photon detecting component is provided. The photon detecting component includes a first waveguide and a detecting section. The detecting section includes a second waveguide; a detector, optically coupled with the second waveguide, configured to detect one or more photons in the second waveguide; an optical switch configured to provide an optical coupling between the first waveguide and the second waveguide when the detector is operational; and an electrical switch electrically coupled to the detector, wherein the electrical switch is configured to change state in response to the detector detecting one or more photons. The photon detecting component further includes readout circuitry configured to determine a state of the electrical switch of the detecting section.

A device including: a semiconductor layer comprising first regions delimited by second regions and third regions; first electrostatic control gates including first conductive portions extending parallel to each other, in vertical alignment with the second regions; second electrostatic control gates including second conductive portions extending parallel to each other, in vertical alignment with the third regions;
wherein each first gate includes an electrostatic control voltage adjustment element forming two impedances connected in series, one end of one of the impedances being coupled to the first conductive portion of the first gate and one end of the other of the impedances being coupled to a third conductive portion applying an adjustment electric potential to the second impedance, and wherein the value of at least one of the impedances is adjustable.

A device including: a semiconductor layer comprising first regions delimited by second regions and third regions; first electrostatic control gates including first conductive portions extending parallel to each other, in vertical alignment with the second regions; second electrostatic control gates including second conductive portions extending parallel to each other, in vertical alignment with the third regions;
wherein each first gate includes an electrostatic control voltage adjustment element forming two impedances connected in series, one end of one of the impedances being coupled to the first conductive portion of the first gate and one end of the other of the impedances being coupled to a third conductive portion applying an adjustment electric potential to the second impedance, and wherein the value of at least one of the impedances is adjustable.

A system and method comprising a cryogenic adiabatic circuit in a cryogenic environment and a clock generator at a higher temperature, the circuit's clock lines can be connected across the temperature gradient to the clock generator, where the clock generator runs below the frequency that would yield power dissipation equal to the static dissipation of a functionally equivalent CMOS circuit at room temperature, resulting in lower power for the function than possible at room temperature irrespective of the speed of operation.

A system and method comprising a cryogenic adiabatic circuit in a cryogenic environment and a clock generator at a higher temperature, the circuit's clock lines can be connected across the temperature gradient to the clock generator, where the clock generator runs below the frequency that would yield power dissipation equal to the static dissipation of a functionally equivalent CMOS circuit at room temperature, resulting in lower power for the function than possible at room temperature irrespective of the speed of operation.

Methods for initializing a qubit into a pure state, reading the qubit, and arbitrarily rotating the qubit into any quantum state complete in times shorter than the qubit's typical dephasing and relaxation times. These methods provide universal single-qubit control and may be used to implement quantum gates with high fidelity. The methods may be implemented with superconducting qubits, such as heavy fluxonium, and do not rely on a three-dimensional cavity for suppressing spontaneous emission. Therefore, the methods may be implemented using smaller two-dimensional architectures commonly used for superconducting circuits. The methods also work with low-frequency qubits, i.e., qubits for which the energy spacing between the two quantum-computational states is less than the mean thermal energy of a surrounding bath. This reduces the cooling requirements of the qubit while maintaining fidelity.

Methods for initializing a qubit into a pure state, reading the qubit, and arbitrarily rotating the qubit into any quantum state complete in times shorter than the qubit's typical dephasing and relaxation times. These methods provide universal single-qubit control and may be used to implement quantum gates with high fidelity. The methods may be implemented with superconducting qubits, such as heavy fluxonium, and do not rely on a three-dimensional cavity for suppressing spontaneous emission. Therefore, the methods may be implemented using smaller two-dimensional architectures commonly used for superconducting circuits. The methods also work with low-frequency qubits, i.e., qubits for which the energy spacing between the two quantum-computational states is less than the mean thermal energy of a surrounding bath. This reduces the cooling requirements of the qubit while maintaining fidelity.

A superconducting DC switch system is provided. The superconducting DC switch system comprises one or more Josephson junctions (JJs), and a magnetic field generator that is configured to switch from inducing a magnetic field in a plane of the one or more JJs, and providing no magnetic field in the plane of the one or more JJs. A DC input signal applied at an input of the one or more JJs is passed through to an output the one or more JJs in the absence of an induced magnetic field, and the DC input signal is substantially suppressed at the output of the one or more JJs in the presence of the magnetic field.

A superconducting DC switch system is provided. The superconducting DC switch system comprises one or more Josephson junctions (JJs), and a magnetic field generator that is configured to switch from inducing a magnetic field in a plane of the one or more JJs, and providing no magnetic field in the plane of the one or more JJs. A DC input signal applied at an input of the one or more JJs is passed through to an output the one or more JJs in the absence of an induced magnetic field, and the DC input signal is substantially suppressed at the output of the one or more JJs in the presence of the magnetic field.