The invention relates to a logic cell for an integrated circuit including at least one first variable-capacitance capacitor having first and second main electrodes separated by an insulating region, and a third control electrode capable of receiving a control voltage referenced to a reference node of the cell to vary the capacitance between the first and second main electrodes, the third electrode being coupled to a node of application of a first logic input signal of the cell, and the first and second electrodes being respectively coupled to a node of application of a cell power supply voltage and to a node for supplying a logic output signal of the cell.

Reduced-power dynamic data circuits with wide-band energy recovery are described herein. In one embodiment, a circuit system comprises at least one sub-circuit in which at least one of the sub-circuits includes a capacitive output node that is driven between low and high states in a random manner for a time period and an inductive circuit path coupled to the capacitive output node. The inductive circuit path includes a transistor switch and an inductor connected in series to discharge and recharge the output node to a bias supply. A pulse generator circuit generates a pulse width that corresponds to a timing for driving the output node.

Aspects of this disclosure are directed to level-shifting approaches with communications between respective circuits. As may be implemented in accordance with one or more embodiments characterized herein, a voltage level of communications passed between respective circuits are selectively shifted. Where the respective circuits operate under respective power domains that are shifted in voltage range relative to one another, the voltage level of the communications is shifted. This approach may, for example, facilitate power-savings for stacked circuits in which a low-level voltage of one circuit is provided as a high-level voltage for another circuit. When the respective circuits operate under a common power domain, the communications are passed directly between the respective circuits (e.g., bypassing any level-shifting, and facilitating fast communication).

Electronic devices employing adiabatic logic circuits with wireless charging are disclosed. In one aspect, an electronic device is provided. The electronic device includes a power circuit employing an alternating current (AC) coupler circuit configured to receive a wireless AC signal and generate a wired AC signal based on the wireless AC signal. The power circuit includes a power output configured to provide an AC power signal based on the wired AC signal generated by the AC coupler circuit. The AC power signal is generated based on the wireless charging capability of the AC coupler circuit. The electronic device employs a digital logic system that includes a power rail electrically coupled to an adiabatic logic circuit. The AC power signal is provided to the power rail to provide power to the adiabatic logic circuit. Wirelessly charging the adiabatic logic circuit consumes less power than conventional non-wireless charging circuitry.

The invention relates to a logic cell for an integrated circuit including at least one first variable-capacitance capacitor having first and second main electrodes separated by an insulating region, and a third control electrode capable of receiving a control voltage referenced to a reference node of the cell to vary the capacitance between the first and second main electrodes, the third electrode being coupled to a node of application of a first logic input signal of the cell, and the first and second electrodes being respectively coupled to a node of application of a cell power supply voltage and to a node for supplying a logic output signal of the cell.

Circuits and methods that use harvested electrostatic energy from transient: on-chip data are described in the Application. In one aspect, a method inverter circuit use harvested electrostatic charge held at any electric potential higher than the common ground reference potential of CMOS circuits in a chip, to partially drive a 0.fwdarw.1 logic transition at the output of the inverter at lower energy drain from the on-chip power grid than a conventional CMOS inverter with similar performance, slew rates at inverter input and output and with similar output driving transistor geometries.

Circuits and methods that harvest electrostatic energy from transient on-chip data are described in the Application. In one aspect, a method inverter circuit harvests electrostatic charge held at its output node at an electric potential comparable to the power supply voltage rail to a common grid/node as the output makes a 0.fwdarw.1 logic transition. This charge harvested at a common gride/node can be used by circuits (described in applications 63/090,169, 63/139,744) to drive 0.fwdarw.1 logic transition at their output nodes at lower energy drain from the on-chip power grid than a conventional CMOS inverter would with similar performance, slew rates at inverter input and output and with similar output driving transistor geometries.

Techniques for charge reuse in an integrated circuit. A processor may include a first logic circuit coupled to a source power supply node, a second logic circuit coupled to a destination power supply node, and a charge reuse circuit that selectively transfers charge from the first logic circuit to the second logic circuit. The charge reuse circuit may include an equalization device that selectively couples the source power supply node to the destination power supply node, and an equalization activation circuit that activates the equalization device in response to detecting assertion of an equalization control signal and further detecting that a voltage differential between the source power supply node and the destination power supply node is above a threshold value. The equalization activation circuit also prevents coupling of either the source power supply node or the destination power supply node to ground during activation of the equalization device.

Aspects of this disclosure are directed to level-shifting approaches with communications between respective circuits. As may be implemented in accordance with one or more embodiments characterized herein, a voltage level of communications passed between respective circuits are selectively shifted. Where the respective circuits operate under respective power domains that are shifted in voltage range relative to one another, the voltage level of the communications is shifted. This approach may, for example, facilitate power-savings for stacked circuits in which a low-level voltage of one circuit is provided as a high-level voltage for another circuit. When the respective circuits operate under a common power domain, the communications are passed directly between the respective circuits (e.g., bypassing any level-shifting, and facilitating fast communication).

A resonant clocking system for reducing wideband series resonant clock skew is provided. The resonant clocking system includes at least one Pulsed Series Resonance (PSR) driver, at least one clock gater, and at least one clock buffer. The PSR driver is connected with at least one on-chip inductor. The PSR driver receives a boosted-amplitude pulsed signal V.sub.SR that is generated using a matching pulse generator and at least one on-chip inductor connected with the at least one Pulsed Series Resonance (PSR) driver resonates with a capacitance of the resonant clocking system to generate a pulse signal R.sub.CLK. The at least one clock gater and the at least one clock buffer propagate the pulse signal R.sub.CLK to clock pins of resonant flip-flops. An inductance value of the at least one on-chip inductor is matched with a load capacitance of a corresponding branch capacitance using an inductor tuning technique to obtain equal frequency signals in all clock branches, thereby storing dissipated energy in a form of a magnetic field in the at least one on-chip inductor and reducing wideband series resonant clock skew.