CIRCUITS AND METHODS TO USE ENERGY HARVESTED FROM TRANSIENT ON-CHIP DATA

Abstract

Circuits and methods that use harvested electrostatic energy from transient: on-chip data are described in the Application. In one aspect, a method inverter circuit use harvested electrostatic charge held at any electric potential higher than the common ground reference potential of CMOS circuits in a chip, to partially drive a 0.fwdarw.1 logic transition at the output of the inverter at lower energy drain from the on-chip power grid than a conventional CMOS inverter with similar performance, slew rates at inverter input and output and with similar output driving transistor geometries.

Claims

1. (canceled)

2. An apparatus, comprising: a power supply voltage terminal configured to provide a power supply voltage; an input terminal; an output terminal; a shared capacitor terminal operatively coupled to the output terminal; and a circuit switch associated with a delay, the circuit switch configured to, responsive to a high-to-low logic transition at the input terminal, sequentially (1) electrically couple then decouple the shared capacitor terminal and the output terminal via a first pulse and (2) electrically couple then decouple the shared capacitor terminal and the output terminal via a second pulse, the second pulse beginning after the first pulse begins and after the delay, the second pulse partially overlapping the first pulse.

3. The apparatus of claim 2, further comprising: a NOR gate including a first input, a second input, and an output, the first input of the NOR gate being the input terminal and the second input of the NOR gate connected to the output terminal.

4. The apparatus of claim 2, further comprising: a NOR gate including a first input, a second input, and an output, the first input of the NOR gate being the input terminal and the second input of the NOR gate connected to the output terminal; and a first NFET including a gate terminal, a source terminal, and a drain terminal, the gate terminal of the first NFET connected to the input terminal, the source terminal of the first NFET connected to reference ground, the drain terminal of the first NFET connected to the output terminal.

5. The apparatus of claim 2, further comprising: a NOR gate including a first input, a second input, and an output, the first input of the NOR gate being the input terminal and the second input of the NOR gate connected to the output terminal; a first NFET including a gate terminal, a source terminal, and a drain terminal, the gate terminal of the first NFET connected to the input terminal, the source terminal of the first NFET connected to reference ground, the drain terminal of the first NFET connected to the output terminal; and a second NFET including a gate terminal, a source terminal, and a drain terminal, the gate terminal of the second NFET connected to the output of the NOR gate, the source terminal of the second NFET connected to the output terminal, the drain terminal of the second NFET connected to the shared capacitor terminal.

6. The apparatus of claim 2, wherein a NOR gate including a first input, a second input, and an output, the first input of the NOR gate being the input terminal and the second input of the NOR gate connected to the output terminal; a first NFET including a gate terminal, a source terminal, and a drain terminal, the gate terminal of the first NFET connected to the input terminal, the source terminal of the first NFET connected to reference ground, the drain terminal of the first NFET connected to the output terminal; a second NFET including a gate terminal, a source, a terminal, and a drain terminal, the gate terminal of the second NFET connected to the output of the NOR gate, the source terminal of the second NFET connected to the output terminal, the drain terminal of the second NFET connected to the shared capacitor terminal; and following the high-to-low logic transition at the input terminal, a leading edge of an active-high pulse at the output of the NOR gate activates the second NFET during operation such that harvested charge on the shared capacitor terminal charges the output terminal raising a voltage at the output terminal above the reference ground.

7. The apparatus of claim 2, further comprising: a NOR gate including a first input, a second input, and an output, the first input of the NOR gate being the input terminal and the second input of the NOR gate connected to the output terminal; a first NFET including a gate terminal, a source terminal, and a drain terminal, the gate terminal of the first NFET connected to the input terminal, the source terminal of the first NFET connected to reference ground, the drain terminal of the first NFET connected to the output terminal; a second NFET including a gate terminal, a source, a terminal, and a drain terminal, the gate terminal of the second NFET connected to the output of the NOR gate, the source terminal of the second NFET connected to the output terminal, the drain terminal of the second NFET connected to the shared capacitor terminal; following the high-to-low logic transition at the input terminal, a leading edge of an active-high pulse at the output of the NOR gate activates the second NFET during operation such that harvested charge on at the shared capacitor terminal discharges the output terminal raising a voltage at the output terminal above the reference ground; and a PFET including a gate terminal, a source terminal, and a drain terminal, the source terminal of the PFET being connected to the power supply voltage terminal and the drain terminal of the PFET being connected to the output terminal.

8. The apparatus of claim 2, further comprising: a NOR gate including a first input, a second input, and an output, the first input of the NOR gate being the input terminal and the second input of the NOR gate connected to the output terminal; a first NFET including a gate terminal, a source terminal, and a drain terminal, the gate terminal of the first NFET connected to the input terminal, the source terminal of the first NFET connected to reference ground, the drain terminal of the first NFET connected to the output terminal; a second NFET including a gate terminal, a source, a terminal, and a drain terminal, the gate terminal of the second NFET connected to the output of the NOR gate, the source terminal of the second NFET connected to the output terminal, the drain terminal of the second NFET connected to the shared capacitor terminal; following the high-to-low logic transition at the input terminal, a leading edge of an active-high pulse at the output of the NOR gate activates the second NFET during operation such that harvested charge on the shared capacitor terminal discharges the output terminal raising a voltage at the output terminal above the reference ground; a PFET including a gate terminal, a source terminal, and a drain terminal, the source terminal of the PFET being connected to the power supply voltage terminal and the drain terminal of the PFET being connected to the output terminal; and an inverter, an input of the inverter connected to the output of the NOR gate, an output of the inverter connected to the gate terminal of the PFET.

9. The apparatus of claim 8, wherein an active high pulse at the input of the inverter during operation causes the PFET to activate for a duration equal to a pulse duration of the active high pulse.

10. The apparatus of claim 8, wherein a propagation delay of the inverter during operation is substantially similar to a time for the output terminal to be charged from the reference ground to a voltage comparable to a voltage at the shared capacitor terminal.

11. The apparatus of claim 8, wherein, during operation, a pulse width of an active high pulse at the output of the NOR gate is comparable to a sum of a propagation delay of the inverter and a time for the PFET to charge the output terminal to a logic threshold voltage of the NOR gate.

12. The apparatus of claim 11, wherein, during operation: the high-to-low logic transition at the input terminal causes the active high pulse at the output of the NOR gate, the active high pulse at the output of the NOR gate causes the second NFET to be activated, and the active high pulse at the output of the NOR gate, delayed by the inverter, causes the PFET to be activated

13. The apparatus of claim 2, further comprising: a PFET including a gate terminal, a source terminal, and a drain terminal, the gate terminal of the PFET connected to the input terminal, the source terminal of the PFET connected to the power supply voltage terminal, and the drain terminal connected to the output terminal.

14. An apparatus, comprising: a power supply voltage terminal configured to provide a power supply voltage; a reference ground voltage terminal; a node (1) operatively coupled to an output terminal and (2) configured to provide a node voltage; an input terminal; and the output terminal.

15. The apparatus of claim 14, further comprising: a NOR gate including a first input, a second input, and an output, the first input of the NOR gate being the input terminal and the second input of the NOR gate connected to the output terminal; a first NFET including a gate terminal, a source terminal, and a drain terminal, the gate terminal of the first NFET connected to the input terminal, the source terminal of the first NFET connected to the reference ground voltage terminal, the drain terminal of the first NFET connected to the output terminal; a second NFET including a gate terminal, a source, terminal, and a drain terminal, the gate terminal of the second NFET connected to the output of the NOR gate, the source terminal of the second NFET connected to the output terminal, the drain terminal of the second NFET connected to the node; a first PFET including a gate terminal, a source terminal, and a drain terminal, the source terminal of the first PFET being connected to the power supply voltage terminal and the drain terminal of the first PFET being connected to the output terminal; an inverter, an input of the inverter connected to the output of the NOR gate, an output of the inverter connected to the gate terminal of the first PFET; and a second PFET including a gate terminal, a source terminal, and a drain terminal, the gate terminal of the second PFET connected to the input terminal, the source terminal of the second PFET connected to the power supply voltage terminal, and the drain terminal of the second PFET connected to the output terminal.

16. The apparatus of claim 15, wherein, during operation, following a high-to-low logic transition at the input terminal, a leading edge of an active-high pulse at the output of the NOR gate activates the second NFET such that harvested charge at the node is discharged to the output terminal.

17. The apparatus of claim 15, wherein an active high pulse at the input of the inverter during operation causes the first PFET to activate for a duration equal to a pulse duration of the active high pulse.

18. The apparatus of claim 15, wherein a propagation delay of the inverter during operation is substantially comparable to a time for the output terminal to be charged from the reference ground voltage terminal to the node voltage.

19. The apparatus of claim 15, wherein, during operation: a high-to-low logic transition at the input terminal causes an active high pulse at the output of the NOR gate, the active high pulse at the output of the NOR gate causes the second NFET to be activated, and the active high pulse at the output of the NOR gate causes the inverter to activate the first PFET.

20. A method, comprising: providing a power supply voltage at a power supply voltage terminal; providing a node voltage at a node operatively coupled to an output terminal; and receiving, at the output terminal, a low-to-high logic transition driven by the node voltage then the power supply voltage following a high-to-low logic transition at an input terminal.

21. The method of claim 20, wherein an energy consumed to drive a low-to-high logic transition at the output terminal is partially provided by the power supply voltage terminal and partially provided by the node.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0013] FIG. 1 is a schematic illustrating conventional CMOS circuit schematic of an inverter and its operation in response to 1.fwdarw.0 and 0.fwdarw.1 input transitions

[0014] FIG. 2 is a circuit simulation: of the conventional CMOS inverter circuit that shows voltage waveforms at the input and at the output terminals of the inverter in response to 1.fwdarw.0 and 0.fwdarw.1 input transitions. The Figure also shows the current waveform that illustrates the current flow dependence on time for the 0.fwdarw.1 transition at the output and the 1.fwdarw.0 transition at the output.

[0015] FIG. 3 is a schematic illustrating the proposed circuit Of an inverter that uses harvested charge held at a grid/node capacitance at any voltage (between the power rails at the supply voltage and the reference ground potential) to drive its output during a 0.fwdarw.1 voltage transition at an energy Cost of 0.6-0.75 of that seen in a conventional CMOS inverter

[0016] FIG. 4 is a circuit simulation of the proposed inverter circuit that uses harvested charge to power the 0.fwdarw.1 voltage transition at its output-showing voltage waveforms at the input and output terminals (that are practically identical to those observed in a conventional CMOS inverter (FIG. 2)) and current waveforms corresponding to current drawn from the grid holding harvested 6harge at VDD/2 and the current drawn from the power rail at voltage=VDD.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0017] FIG. 1 is a schematic illustrating operation of a conventional CMQS inverter 100 driving output node OUT 102 with a capacitive load C.sub.out 104. The power rail 106 at electric potential V.sub.DD provides total energy equal to C.sub.out V.sub.DD.sup.2 (derived in equation (1) below) during a 0.fwdarw.1 transition 108 at the output node OUT 102, storing energy of ()C.sub.outV.sub.DD.sup.2 on the capacitor 104 at the output 102 modeled by equation (2) below. A 1.fwdarw.0 112 transition at the output 102 discharges from C.sub.out 104 all of this stored energy on the capacitor C.sub.out 104 at the output 102 to the reference ground node 110 at electric potential Vss=0V

Energy Drawn from VDD Supply (During 0.fwdarw.1 Transition at Output)

[00001]$\begin{array}{cc}\text{?}=\text{?}=\text{?}& \left(1\right)\end{array}$$\text{?}\text{indicates text missing or illegible when filed}$

Energy Stored at Output

[00002]$\begin{array}{cc}\text{?}=\text{?}=\text{?}& \left(2\right)\end{array}$$\text{?}\text{indicates text missing or illegible when filed}$

Energy Discharged from Output (During 1.fwdarw.0 Transition at Output)

[00003]$\begin{array}{cc}\text{?}=\text{?}=\text{?}& \left(3\right)\end{array}$$\text{?}\text{indicates text missing or illegible when filed}$

[0018] FIG. 2 200 is an illustration of the time dependent voltage waveforms of the output node OUT (102 in FIG. 1 100) shown as the waveform V.sub.out 202 in FIG. 2. The voltage waveform driving the input of the inverter 118 in FIG. 1, is shown in FIG. 2 as V.sub.IN 204

[0019] The waveform of current flow 206 into the inverter from the power rail at voltage V.sub.DD (106 in FIG. 1) is shown along the same x-axis of time (as used to plot voltage waveforms) in FIG. 2. The absolute value of the integral of the current waveform 206 over time in FIG. 2 200 equals the total charge Q drained from the Power rail (106 in FIG. 1) to drive the output node 102 from 0.fwdarw.1. The energy consumed from the power rail 106 to accomplish this logic transition at the output node 102 equals [Q.Math.Vss]=C.sub.outV.sub.DD.sup.2 modeled in equation (1) above.

[0020] In FIG. 3 the proposed circuit schematic functioning as an inverter 300 shows: a 2-input NOR 302 and a delay element 304 that also inverts. The 2-input NOR 302 and the delay element 304 have devices with much smaller widths ( of driver transistors) than the other transistors (326,314,320) in this schematic 300.

[0021] The NOR gate 302 in this schematic generates an active high pulse at its output node 306 whose leading edge is triggered by a 1.fwdarw.0 transition at the input 308 and whose trailing edge is triggered by a 0.fwdarw.1 transition at the output node 310 loaded with a total capacitance C.sub.OUT 312.

[0022] The leading edge of this active high pulse turns on NFET N2 314 which drives charge harvested on the V2 node 316 (held at a voltage typically between VSS and VDD and preferably at a voltage comparable to the logic threshold of the NOR gate 302) to the output node 310 of this inverter.

[0023] The leading edge of the, active high pulse at the output of the NOR gate 306, when delayed and inverted to drive the gate input 318 of PFET Pl 320, turns on PFET P1 320 to begin charging the output 310 to V.sub.DDas the output voltage at node OUT 310 approaches V2. Note that a design requirement on the logic threshold voltage of the NOR gate 302 is that it is lower than the typical voltage node V2 would be raised to with harvested charge. Thus, node OUT 310 when being charged to V2 through NFET N2 314, can trip the NOR 302 to produce the high.fwdarw.low transition of the active high pulse at output of the NOR gate 306 to turn-off N2 314.

[0024] The NOR 302 would also trip when the P channel FET P1 320 begins conducting after the delayed and inverted leading edge of the active high pulse output from the NOR turns on P1 320.

[0025] The output terminal continues being charged to VDD by the power rail 324 as P1 320 is turned on. The trailing edge of the active low pulse driving the gate input terminal of the P channel FET 320 turns this PFET 320 off. A small geometry keeper HVT PFET 328 holds the output to V.sub.DD. Its gate input is driven by the inverter input 308 with its source terminal connected to the power rail 324 at voltage V.sub.DD and its drain terminal connected to OUT 310.

[0026] The trailing edge of the active high pulse at the output of the NOR 306 is triggered by the transition at the output node from 0.fwdarw.V2 since the logic threshold of the NOR 302 is less than the voltage at which node V2 316 is charged to with harvested charge, the trailing edge is triggered by this feedback from OUT 310 to the output of the NOR 306.

[0027] The proposed circuit (1) maintains rail-rail operation (2) drives practically the same waveforms at its output as a conventional inverter and (3) uses about 25%-40% of the total charge it drives to its output 310from the harvest grid node V2 316, instead of getting that charge from the VDD supply rail 324. The primary overhead in area is consumed by the NFET N2 in FIG. 3. All of the other transistors in FIG. 3 are small and can be replaced by equivalent standard cells. Transistors Pl 320, NI 326 in FIG. 3 are identical to the transistors 116 and 114 in the schematic of the inverter in FIG. 1 100.

[0028] The NOR gate 302 and the delay element 304 can be optimized to maximize the energy used from the grid/node holding harvested charge according to what voltage the harvested charge is typically held at when using the proposed inverter. The closer the voltage of the harvested charge is to VDD, the higher the optimal logic threshold voltage of the NOR gate 302 is optimized at and the longer the delay value of the delay element 304 needs to be to maximize the use of harvested charge to accomplish the same 0.fwdarw.1 transition at the output of the inverter. This optimization is especially useful when operating at low, near threshold voltages

[0029] FIG. 4 400 is an illustration of the time dependent voltage waveforms Of the output node OUT (310 in FIG. 3) shown as V.sub.OUT 402 in FIG. 4. The input waveform driving the input 308 of the inverter in FIG. 3, V.sub.IN 404 is also shown in FIG. 4

[0030] The waveform of current flow 406 into the inverter from toe VDD power rail (324 in FIG. 3) is shown along the same x-axis (as used to plot voltage waveforms) in FIG. 4. The absolute value of the integral of Current over time in FIG. 4 400 equals the total charge Q drained from the power rail (324 in FIG. 3) to drive the output from 0.fwdarw.1. Note that initially the charge to drive the output in the 0.fwdarw.1 transition comes from the harvest charge grid/node V2 316 in FIG. 3. The total charge driven to node OUT 310 in FIG. 3 is the total area under the curves 406 and 408 in FIG. 4. This sum approximately equals the area under the current waveform 206 in FIG. 2 for the conventional CMOS inverter. Note that the voltage waveform at the output node 310 in FIG. 3 is practically the same as the voltage waveform of the output node 102 in FIG. 1 100 of a conventional inverter. However, for the schematic in FIG. 3 300 the total charge consumed from the power rail to complete the 0.fwdarw.1 transition at the output node 310 is only 60%-75% of the total charge taken from the power rail 106 in FIG. 1 for a conventional CMOS inverter. Total current in the comparison is based on simulation of the entire circuit shown in FIG. 1 100 and FIG. 3 300and thus includes parasitic contributions of all transistors to circuit operation. All parasitic capacitances Of transistors in the complete schematic contribute to slew rate seen at the output and overheads incurred in propagation delay in the schematic

[0031] Switching energy Consumption by logic gates with low fanouts (<4) are typically small. Gates driving a high fanout (>10) and/or long wires consume more energy and are best candidates for the proposed scheme that uses harvested charge.

[0032] The transistor energy increases in the proposed schematic shown in FIG. 3 300 compared to the 2 transistors used in a conventional CMOS inverter. However, the area consume by the proposed schematics in FIG. 3 300 does not increase proportionally with the number of translators because the transistors of gates (302, 304 in FIG. 3) are 5 smaller than any of the transistors (326, 314 and 320 in FIG. 3 300). This because the load seen by the NOR gate 302 is small-essentially just the gate input, of a single NTFT (N2 314 in FIG. 3)with the load from the delay element 304 much smaller. The transistors P1 320, N1 326 and N2 314 in FIG. 3 are comparable (in dimensions) to the transistors P1 114 and N1 116 in a conventional CMOS inverter shown in FIG. 1 100 that drives the same capacity load C.sub.OUT 104 in FIGS. 1 and 312 in FIG. 3. The gate footprint of the proposed schematic 300 (in FIG. 3) is not expected to be larger than 1.7-2.0 of the CMOS inverter it replaces. Note that the proposed schematics are preferred as replacement candidates of CMOS inverters only when driving large loadsthat offer the opportunity for larger energy reductions.

[0033] Although illustrative embodiments of the present invention have been described herein, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modification may be made by one skilled in the art without departing from-the scope of the invention.