A differential delay between a non-inverted output and an inverted output of a transistor circuit is reduced.

A transistor circuit includes a first transistor and a second transistor. The first transistor receives an input signal as an input, and outputs a first output signal. The second transistor receives the input signal as an input, and outputs a second output signal, which is in a reverse polarity with respect to the first output signal, on the basis of a bias that causes the second transistor to operate in a complementary manner with respect to the first transistor. The first transistor may include a first terminal, a second terminal, and a first control terminal that controls a current that flows between the first terminal and the second terminal. The second transistor may include a third terminal, a fourth terminal, and a second control terminal that controls a current that flows between the third terminal and the fourth terminal. The first output signal may be output from the first terminal, the second output signal may be output from the third terminal, and the input signal may be input to the second terminal of the first transistor and the second control terminal of the second transistor.

According to one embodiment of the present disclosure, a circuit includes a Correlated Electron Switch (CES) element and a programming circuit. The CES element includes a first input. The first input of the CES element is coupled to an input signal to be monitored. The CES element is programmed in a first impedance state. The programming circuit coupled to the CES element is configured to switch the CES element from the first impedance state to a second impedance state in response to a voltage transition on the input signal. The voltage transition indicates a fault event. The output element coupled to the first input of the CES element determines that the transition has occurred responsive to the CES element switching to the second impedance state.

A semiconductor apparatus may include a noise determination circuit, a strobe signal control circuit, and a reception circuit. The noise determination circuit may sense and determine noise of a reference voltage, and generate an up control signal and a down control signal. The strobe signal control circuit may adjust a transition timing of a strobe signal in response to the up control signal and the down control signal, and output a control strobe signal. The reception circuit may generate internal data signal in response to external data signal, the reference voltage, and the control strobe signal.

An electronic circuit includes: a first logic circuit coupled to a first input line and a first output line; a second logic circuit coupled to a second input line and a second output line; a first line pattern coupled to the first output line and including an input line different from the second input line; and a second line pattern coupled to the second output line and different from the first input line, wherein at least a part of the first output line, the first line pattern, the second output line, or the second line pattern has a folded shape or a circular shape.

A method for optimizing an implementation of a logic circuit, comprising steps of providing an interpretation of the logic circuit in terms of 3 Boolean variable majority operators M, with each of the majority operators being a function of a plurality of variables that returns a logic value assumed by more than half of the plurality of variables, and a single Boolean variable complementation operator . The method further comprises providing a commutativity, a majority (.M), an associativity (.A), a distributivity (.D), an inverter propagation (.I), a relevance (.R), a complementary associativity (.C), and a substitution (.S) transformation; and combining the .M, .C, .A, .D, .I, .R, .C and .S transformations to reduce an area of the logic circuit via (i) a reshaping procedure consisting of the .A, .C, .D, .I, .R, .S and .C transformations, applied either left-to-right or right-to-left moving identical or complemented variables in neighbor locations of the logic circuit, (ii) an elimination procedure consisting of the .M transformation, applied left-to-right, and the .D transformation, applied right-to-left, that simplify redundant operators, or (iii) an iteration of steps (i) and (ii) till a reduction in area is achieved.

A semiconductor integrated circuit includes a plurality of semiconductor chips stacked in a multi-layer structure; a correction circuit in each semiconductor chip configured to reflect a delay time corresponding to the position of the chip in the stack into an input signal to output to each semiconductor chip; and a plurality of through-chip vias formed vertically through each of the semiconductor chips and configured to transmit the input signal to the semiconductor chip.

According to one embodiment, a semiconductor device includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first level shifter, and a second level shifter. At a time of outputting a first voltage from a first terminal, a power supply voltage is supplied to the first terminal from the third transistor in accordance with a fourth signal output from the second level shifter, and then the first voltage is supplied to the first terminal from the first transistor in accordance with a second signal output from the first level shifter. At a time of outputting a second voltage from the first terminal, a ground voltage is supplied to the first terminal from the fourth transistor in accordance with the second signal, and then the second voltage is supplied to the first terminal from the second transistor in accordance with the fourth signal.

There is provided a CMOS inverter circuit device. The CMOS inverter circuit device includes a delay circuit unit configured to generate different charge and discharge paths of each gate node of a PMOS transistor and an NMOS transistor respectively at the time that an input signal transitions between high and low levels. Therefore, the present examples minimize or erase generation of a short circuit current made at the time that the input signal transition. The examples may simplify circuit architecture, and may make a magnitude of a CMOS inverter circuit device smaller.

According to one embodiment of the present disclosure, a circuit includes a Correlated Electron Switch (CES) element and a programming circuit. The CES element includes a first input. The first input of the CES element is coupled to an input signal to be monitored. The CES element is programmed in a first impedance state. The programming circuit coupled to the CES element is configured to switch the CES element from the first impedance state to a second impedance state in response to a voltage transition on the input signal. The voltage transition indicates a fault event. The output element coupled to the first input of the CES element determines that the transition has occurred responsive to the CES element switching to the second impedance state.

A driver device is for switching on and off a transistor for supplying a load by driving a control electrode of the transistor. The driver device includes a first terminal connected to the control electrode of the transistor, a second terminal connected between the transistor and the load, and a current-discharge path coupled to the first terminal. The current-discharge path includes a diode and is activated when the transistor is switched off. The diode becomes non-conductive to interrupt the current-discharge path when the voltage on the second terminal reaches a threshold value.