An asynchronous circuit may include a single-rail logic datapath; one or more error-detecting latches; a controller that controls the error-detecting latches; and delay lines. The controller and the delay lines may cooperate to communicate with one or more other controllers that the output of the controlled error-detecting latches may be valid prior to when the error-detecting latches indicate whether or not an error occurred.

A multi-channel digital isolator includes a digital isolator and an interlock circuit. The isolator includes a transmitter having a transmitter output, a receiver having a receiver input and a receiver output, an isolation barrier coupled between the transmitter output and the receiver input, and an output buffer having a buffer input and configured to output an isolated signal. The transmitter is configured to transmit an input signal across the isolation barrier. The interlock circuit has an interlock input coupled to the receiver output and an interlock output coupled to the buffer input. The interlock module is configured to prevent overlapping active states between the first isolated signal and a complementary isolated signal. In some implementations, the digital isolator also includes a dead-time insertion circuit.

Embodiments provide a power supply switching circuit, which generates a first control signal jointly by utilizing a first input signal and a first drive signal opposite in phase to a second control signal, and generates the second control signal jointly by utilizing a second input signal and a second drive signal opposite in phase to the first control signal, such that time (i.e., overlap time) required for simultaneously turning on or off a first output subcircuit and a second output subcircuit is greatly reduced or even eliminated, effective output of an output node is implemented, and reliability of a device is improved. Furthermore, compared with eliminating the overlap time by means of delay, eliminating the overlap time by means of the power supply switching circuit is simple and reliable in control logic and is insensitive to process, which further improves the reliability of the device.

An active gate driver provided to drive a power transistor includes a two-level Miller plateau detector, a cycle shifter, a flexible split-path feedback circuit, a PMOS switch picker, a NMOS switch picker, a PMOS buffer array and a NMOS buffer array. The active gate driver turns off some PMOS transistors of the PMOS buffer array and some NMOS transistors of the NMOS buffer array to lower power consumption when the power transistor in the Miller plateau. And the active gate driver also turns off some PMOS transistors of the PMOS buffer array if a gate-source voltage is greater than a high-potential reference voltage, thereby further reducing power consumption.

According to one embodiment, a semiconductor device includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first level shifter, and a second level shifter. At a time of outputting a first voltage from a first terminal, a power supply voltage is supplied to the first terminal from the third transistor in accordance with a fourth signal output from the second level shifter, and then the first voltage is supplied to the first terminal from the first transistor in accordance with a second signal output from the first level shifter. At a time of outputting a second voltage from the first terminal, a ground voltage is supplied to the first terminal from the fourth transistor in accordance with the second signal, and then the second voltage is supplied to the first terminal from the second transistor in accordance with the fourth signal.

Implementations of a pre-emphasis signal processing system may include an output driver which may include a pre-emphasis transistor coupled with a steady state transistor, where gates of the pre-emphasis transistor and steady state transistor may be coupled together. The system may include a regulator voltage input coupled to a source of the pre-emphasis transistor; a first resistor coupled between a drain of the pre-emphasis transistor and an output of the output driver; and a second resistor coupled between the drain of the steady state transistor and the output of the output driver; and a pre-emphasis source including a current source coupled to a delay transistor, the delay transistor coupled with the output of the output driver.

An active gate driver provided to drive a power transistor includes a two-level Miller plateau detector, a cycle shifter, a flexible split-path feedback circuit, a PMOS switch picker, a NMOS switch picker, a PMOS buffer array and a NMOS buffer array. The active gate driver turns off some PMOS transistors of the PMOS buffer array and some NMOS transistors of the NMOS buffer array to lower power consumption when the power transistor in the Miller plateau. And the active gate driver also turns off some PMOS transistors of the PMOS buffer array if a gate-source voltage is greater than a high-potential reference voltage, thereby further reducing power consumption.