An interconnection network for providing data transfer between a plurality of nodes of an integrated circuit comprises a number of endpoints for exchanging data with respective nodes of the integrated circuit, a primary network to route a primary payload from a source endpoint to a destination endpoint; and a redundant network to route, to the destination endpoint, a redundant payload comprising a first check code calculated based on at least a portion of the primary payload, the first check code having fewer bits than said at least a portion of the primary payload. The destination endpoint comprises error checking circuitry to perform an error checking operation to calculate a second check code based on the primary payload received via the primary network, and verify integrity of the primary payload based on a comparison of the second check code with the first check code received via the redundant network.

An apparatus and method for transmitting signals between two clock domains in which at least one of a phase and a frequency of clock signals in the two clock domains is misaligned. The apparatus includes a first primary interface and a first redundant interface in the first clock domain for receiving a primary signal and a first checking signal respectively, and a second primary interface and second redundant interface in the second clock domain for outputting the primary signal and a second redundant signal respectively. The primary signal and the checking signals are separated by a predetermined time delay and the second checking signal is generated in the second clock domain based on the primary signal. Checking circuitry is provided in the second clock domain to perform an error checking procedure based on the two checking signals and to provide the second checking signal to the second redundant interface.

Systems, methods, and apparatus for complementary self-limiting logic are disclosed. In one or more embodiments, a method for mitigating errors caused by transients in a logic gate transistor comprises biasing, by a first stage of transistors, a second stage of transistors such that a voltage potential across terminals of each of the transistors of the second stage are at an equal voltage potential. The method further comprises biasing, by the second stage of transistors, the logic gate transistor such that a voltage potential across terminals of the logic gate transistor are at an equal voltage potential, thereby ensuring that the transients will not cause the logic gate transistor to erroneously change logic states when the logic gate transistor is in a logically off state.

An LVDS device wherein driver and receiver functionalities are integrated in the same package, signals are routed from the individual driver and receiver elements inside the package such that all inputs are one side of the package, and all outputs are on the opposite side of the package, allowing for an optimized signal flow through the package. All required capacitors and resistors are integrated inside the package; no external electronic components are required. All of the above novelties also contribute to a 6:1 reduction in size compared to current state-of-the-art, for the same number of communication channels. Embodiments include a packaging topology adaptable to extreme environments, including radiation tolerant to 300 kRad (based on the die technology), so that module operational temperature is in a range of 55 C. to +100 C. and storage temperature can be as low as 184 C.

The present invention relates to a single board computer system with an improved memory and layout. The unique layout of the printed circuit board of the present invention allows for different parts to be placed in a back-to-back configuration to minimize the dimensions of the printed circuit board. This includes a high-performance radiation-hardened reconfigurable FPGA, for processing computation-intensive space systems, disposed on both sides of the printed circuit board. Four dual double data rate synchronous dynamic random-access memories (DDR2 SDRAMs) disposed on both the top side and on the bottom side of the printed circuit board reduce an operating voltage of said printed circuit board. A layout stack-up of the printed circuit board includes twenty-two symmetrical layers including ten ground layers, four power layers, six signal layers, a top layer, and a bottom layer.

The invention is a microcircuit configured as a compact, radiation hardened, low-power general purpose I/O expander. The expander may be controlled by an external microcontroller or central processing unit through a serial interface. The expander provides a simple solution to miniaturize static parallel I/O signals using a simplified serial interface such as I.sup.2C or SPI.

According to embodiments of the present invention, a circuit is provided. The circuit includes forming a first electrical device having a first region of a first conductivity type, forming a second electrical device having a second region of a second conductivity type, and electrically coupling the first region and the second region to each other, wherein one of the first and second regions is arranged to at least substantially surround the other of the first and second regions. According to further embodiments of the present invention, a method of forming a circuit is also provided.

A synchronization circuit includes a first synchronizer, a second synchronizer, and selection circuitry. The first synchronizer is configured to synchronize a received signal to a clock signal. The second synchronizer is disposed in parallel with the first synchronizer and configured to synchronize the received signal to the clock signal. The selection circuitry is coupled to the first synchronizer and the second synchronizer. The selection circuitry is configured to provide an output value generated by the first synchronizer at an output terminal of the synchronization circuit based on the output value generated by the first synchronizer being the same as an output value generated by the second synchronizer.

An integrated circuit system includes: a storage element which stores in advance a plurality of pieces of circuit information and startup control circuit information used to configure a startup control logic circuit for selecting circuit information that has not failed in configuring a logic circuit; and an integrated circuit which, at the time of startup or when configuration of the logic circuit based on any of the plurality of pieces of circuit information has failed, configures the startup control logic circuit by reading the startup control circuit information from the storage element, causes the configured startup control logic circuit to select the circuit information that has not failed in configuring the logic circuit, reads the circuit information selected by the startup control logic circuit from the storage element, and configures the logic circuit according to the circuit information.

Provided is a Precision Voltage Reference (PVR). In one example, the PVR includes a resonator having an oscillation frequency, the resonator including a first proof-mass, a first forcer located adjacent a first side of the first proof-mass, and a second forcer located adjacent a second side of the first proof-mass. The PVR may include control circuitry configured to generate a reference voltage based on the oscillation frequency of the resonator, at least one converter configured to receive the reference voltage from the control circuitry, provide a first bias voltage to the first forcer based on the reference voltage, provide a second bias voltage to the second forcer based on the reference voltage, and periodically alter a polarity of the first and second bias voltages to drive the oscillation frequency to match a reference frequency, and an output configured to provide the reference voltage as a voltage reference signal.