A logic circuit includes a setting circuit which holds and outputs setting information, a first flip-flop which holds data written to the setting circuit and outputs it in synchronization with an inputted clock, a second flip-flop which holds a write address for selecting the setting circuit and outputs it in synchronization with the inputted clock, and a third flip-flop which holds write enable which allows writing to the setting circuit and outputs it in synchronization with the inputted clock, wherein the setting circuit includes a fourth flip-flop which holds the setting information in synchronization with a given timing signal, and a fifth flip-flop which holds the output of the third flip-flop and outputs a write clock to the fourth flip-flop as the timing signal in synchronization with the inputted clock.

Integrated circuits with single event upset (SEU) detection circuitry are provided. The SEU detection circuitry may include an error detection block for detecting soft errors and a sensitivity processor that determines whether or not to correct the detected soft errors. The sensitivity processor may be used to access a sensitivity map header (SMH) file that is stored on external memory. The sensitivity map header file contains information that can help identify which logic region on the integrated circuit the soft error affects and whether or not that soft error can critically cause functional failure for the integrated circuit. Depending on the criticality of the soft error, different corrective actions may be taken.

The present invention relates to a compact, low power, radiation-hardened-by-design 8-channel analog multiplexer ASIC, a 0.25 m complementary metal-oxide semiconductor (CMOS); a 500 krad total ionization dose and single event latchup which is greater than the linear energy transfer (LET) 120 MeV-sq. cm/mg; eight channels for 8-to-1 multiplexing; a three nanosecond break-before-make decoder; an active low enable pin; and an on-resistance of less than 500 ohms from input to output pads.

A system for detecting radiation events, having: a test memory with memory blocks; a controller having controller memory; an integrated circuit (IC) array having IC chains, wherein each of the IC chains has a plurality of IC elements that is response to and generates a voltage when exposed to a radiation event; a dosimeter configured to record an accumulated amount of radiation exposure to the system, wherein the controller is configured to perform steps of: initializing the test memory, the IC array and the dosimeter; monitoring for an unexpected signal from an IC chain and for unexpected data in a memory block of the test memory; and identifying the radiation event upon one or more of receiving the unexpected signal and identifying unexpected data in a memory block of the test memory.

A latchup detector includes a level shifter and a comparator. The level shifter is electrically coupled to a voltage supply rail to receive as inputs a regulator output voltage and a target supply voltage. The level shifter includes a first level-shifter circuit that lowers the regulator output voltage to a first voltage and a second level-shifter circuit that lowers the target supply voltage to a second voltage. The comparator receives as inputs the first and second voltages. The comparator produces a first output voltage when the difference between the first and second voltages is greater than or equal to a predetermined voltage difference and a second output voltage when the difference between the first and second voltages is less than the predetermined voltage difference. The first output voltage can correspond to a latchup event.

A latchup detector includes a level shifter and a comparator. The level shifter is electrically coupled to a voltage supply rail to receive as inputs a regulator output voltage and a target supply voltage. The level shifter includes a first level-shifter circuit that lowers the regulator output voltage to a first voltage and a second level-shifter circuit that lowers the target supply voltage to a second voltage. The comparator receives as inputs the first and second voltages. The comparator produces a first output voltage when the difference between the first and second voltages is greater than or equal to a predetermined voltage difference and a second output voltage when the difference between the first and second voltages is less than the predetermined voltage difference. The first output voltage can correspond to a latchup event.

A single event upset (SEU) hardened flip-flop comprises a master latch and a plurality of slave latches, where an output of the master latch is coupled to a respective input of the slave latches. A Muller element which has an input which is coupled to a respective output of the slave latches and an output which is coupled to a bus keeper. The bus keeper maintains a logic level output in presence of the SEU.

A semiconductor component includes a substrate including a plurality of source/drain implants in the form of rows and a charge storage structure disposed over the substrate. The charge storage structure includes at least three continuous layers including a first silicon oxide layer, a silicon nitride layer disposed on the first silicon oxide layer, and a second silicon oxide layer disposed on the silicon nitride layer. The semiconductor component further includes a plurality of gate structures in the form of columns disposed over the charge structure and extending perpendicular to the rows and further includes a radiation protection layer disposed over the charge storage structure and the plurality of gate structures. The radiation protection layer includes a radiation resistant material including boron having an isotope composition of at least 90% boron-11.

The present disclosure is directed to a programmable logic device, such as a field programmable gate array (FPGA), that can withstand and operate in high radiation environments. The programmable logic device includes a bit line, a first logic gate coupled to the bit line, and a second logic gate coupled to the first logic gate and the bit line. The programmable logic device further includes a magnetoresistive memory circuitry coupled to the first logic gate and the second logic gate, the magnetoresistive memory circuitry including a non-volatile memory element and a latch. A third logic gate is coupled to the latch, a multiplexer (MUX) is coupled to the third logic gate and the bit line, and a tri-gate is coupled to the third logic gate, the MUX, and the bit line.