A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. Input signals in the form of digital signals are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node which provides a majority function of the inputs. The majority node is then coupled driver circuitry which can be any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. In the multi-input majority or minority gates, the non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels. Bringing the majority output close to rail-to-rail voltage eliminates the high leakage problem faced from majority gates formed using linear input capacitors.

A circuit includes a first delay filter, a first comparator, an inverter, a second delay filter, a second comparator, an OR gate, and a latch. A first delay filter input is coupled to an inverter input. The first comparator has a first comparator input coupled to a first delay filter output and a second comparator input. The second delay filter has an input coupled to an inverter output. The second comparator has a third comparator input coupled to a second delay filter output, and a fourth comparator input coupled to the second comparator input. The OR gate has an input coupled to a first comparator output and another input coupled to a second comparator output. The latch has a clock input coupled to an OR gate output and a latch input coupled to the inverter input. A latch output provides a deglitched signal.

An example apparatus includes: a switch having a first current terminal, a second current terminal and a control terminal, the first current terminal adapted to be coupled to a first capacitor, the second current terminal adapted to be coupled to a second capacitor; a comparator having a comparator input and a comparator output, the comparator input coupled to a configuration terminal; a deglitch circuit having a deglitch input and a deglitch output, the deglitch input coupled to the comparator output, the deglitch circuit having a deglitch duration between a first duration and a second duration; and a universal serial bus (USB) controller having a controller output and a controller input, the controller output coupled to the control terminal, the controller input coupled to the deglitch output.

A slew rate control circuit is disclosed. The slew rate control circuit includes an input port to receive an input signal, a transmitter to transmit the input signal to an output port and an impedance control circuit coupled between the transmitter and the output port. The impedance control circuit has an adjustable impedance that is configured to be adjusted during a rise and a fall of the input signal using a trim code and an one shot pulse.

It is an objective to provide an arrangement for reducing qubit leakage errors in a quantum computing system. According to an embodiment, an arrangement for reducing qubit leakage errors includes a first qubit and a second qubit selectively couplable to each other. The arrangement also includes an energy dissipation structure that is selectively couplable to the first qubit. The energy dissipation structure is configured to dissipate energy transferred from the first qubit. The arrangement further includes a control unit configured to perform a first quantum operation to transfer a property of a quantum state from the first qubit to the second qubit, couple the first qubit to the energy dissipation structure for a time interval, and perform a second quantum operation to transfer the property of the quantum state from the second qubit to the first qubit after the time interval.

A debounce circuit and a method for masking or filtering a glitch from an input signal are provided. The debounce circuit includes a reset synchronizer circuit and a logic circuit. The reset synchronizer circuit receives the input signal, detects a glitch in the input signal and outputs one or more reset synchronizer output signals having a first reset synchronizer state indicating detection of the glitch. The logic circuit receives the one or more reset synchronizer output signals, determines that the one or more reset synchronizer output signals are in the first reset synchronizer state indicating detection of the glitch and in response to determining that the one or more reset synchronizer output signals are in the first reset synchronizer state, keeps an output signal of the debounce circuit in a present state of the output signal of the debounce circuit.

An arrangement, an apparatus, a quantum computing system, and a method are disclosed for reducing qubit leakage errors. In an example, an apparatus includes a qubit having a ground state and a plurality of excited states. The plurality of excited states include a lowest excited state. An energy difference between the ground state and the lowest excited state corresponds to a first frequency, and an energy difference between the lowest excited state and another excited state in the plurality of excited states corresponds to a second frequency. The apparatus also includes an energy dissipation structure to dissipate transferred energy, and a filter having a stopband and a passband. The filter is coupled to the qubit and to the energy dissipation structure. The stopband includes the first frequency and the passband includes the second frequency for reducing qubit leakage errors.

To provide a novel shift register. Transistors 101 to 104 are provided. A first terminal of the transistor 101 is connected to a wiring 111 and a second terminal of the transistor 101 is connected to a wiring 112. A first terminal of the transistor 102 is connected to a wiring 113 and a second terminal of the transistor 102 is connected to the wiring 112. A first terminal of the transistor 103 is connected to the wiring 113 and a gate of the transistor 103 is connected to the wiring 111 or a wiring 119. A first terminal of the transistor 104 is connected to a second terminal of the transistor 103, a second terminal of the transistor 104 is connected to a gate of the transistor 101, and a gate of the transistor 104 is connected to a gate of the transistor 102.

An apparatus includes a main core processor configured to receive a first signal through a first main buffer, a second signal through a second main buffer, a third signal through a third main buffer, and a fourth signal through a fourth main buffer, a shadow core processor configured to receive the first signal through a first shadow buffer, the second signal through a second shadow buffer, the third signal through a third shadow buffer and the fourth signal through a fourth shadow buffer, and a first glitch suppression buffer coupled to a common node of an input of the first main buffer and an input of the first shadow buffer.

A local oscillator buffer circuit comprises a complementary common-source stage comprising a first p-channel transistor (MCSP) and a first n-channel transistor (MCSN), arranged such that their respective gate terminals are connected together at a first input node, and their respective drain terminals of each of is connected together at a buffer output node. A complementary source-follower stage comprises a second p-channel transistor (MSFP) and a second n-channel transistor (MSFN), arranged such that their respective gate terminals are connected together at a second input node, and their respective source terminals are connected together at the buffer output node.