An arrangement, an apparatus, a quantum computing system, and a method are disclosed for reducing qubit leakage errors. In an example, an apparatus includes a qubit having a ground state and a plurality of excited states. The plurality of excited states include a lowest excited state. An energy difference between the ground state and the lowest excited state corresponds to a first frequency, and an energy difference between the lowest excited state and another excited state in the plurality of excited states corresponds to a second frequency. The apparatus also includes an energy dissipation structure to dissipate transferred energy, and a filter having a stopband and a passband. The filter is coupled to the qubit and to the energy dissipation structure. The stopband includes the first frequency and the passband includes the second frequency for reducing qubit leakage errors.

A data transmission circuit, a data transmission method and an electronic device are provided. The data transmission circuit includes a data processing circuit and a data driving circuit. The data processing circuit is configured to receive a first data signal in a parallel state and convert the first data signal into a second data signal in a serial state. The data driving circuit includes a driving main circuit and a driving regulation circuit. The driving regulation circuit is configured to reduce, in response to the driving regulation circuit being in an enabled state, a voltage difference of the second data signal, to shorten a charging and discharging time and implement driving enhancement. The driving main circuit is configured to perform driving on an enhanced second data signal to obtain a target transmission signal.

This application relates to control of semiconductor devices, in particular MOS devices, so as to reduce RTS/flicker noise. A circuit (100) includes a first MOS device (103, 104) and a bias controller (107). The circuit is operable in at least a first circuit state (P.sub.RO) in which the first MOS device is active to contribute to a first signal (Sout) and a second circuit state (P.sub.RST) in which the first MOS device does not contribute to the first signal. The bias controller is operable to control voltages at one or more terminals of the first MOS device to apply a pre-bias (V.sub.PB1, V.sub.PB2) during an instance of the second circuit state. The pre-bias is applied to set an occupancy state of charge carriers traps within the first MOS device, to limit noise during subsequent operation in the first circuit state. In embodiments, the bias controller is configured so that at least one parameter of the pre-bias is selectively variable in use based on one or more operating conditions.

A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. Input signals in the form of digital signals are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node which provides a majority function of the inputs. The majority node is then coupled driver circuitry which can be any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. In the multi-input majority or minority gates, the non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels. Bringing the majority output close to rail-to-rail voltage eliminates the high leakage problem faced from majority gates formed using linear input capacitors.

A circuit includes a first delay filter, a first comparator, an inverter, a second delay filter, a second comparator, an OR gate, and a latch. A first delay filter input is coupled to an inverter input. The first comparator has a first comparator input coupled to a first delay filter output and a second comparator input. The second delay filter has an input coupled to an inverter output. The second comparator has a third comparator input coupled to a second delay filter output, and a fourth comparator input coupled to the second comparator input. The OR gate has an input coupled to a first comparator output and another input coupled to a second comparator output. The latch has a clock input coupled to an OR gate output and a latch input coupled to the inverter input. A latch output provides a deglitched signal.

An arrangement, an apparatus, a quantum computing system, and a method are disclosed for reducing qubit leakage errors. In an example, an apparatus includes a qubit having a ground state and a plurality of excited states. The plurality of excited states include a lowest excited state. An energy difference between the ground state and the lowest excited state corresponds to a first frequency, and an energy difference between the lowest excited state and another excited state in the plurality of excited states corresponds to a second frequency. The apparatus also includes an energy dissipation structure to dissipate transferred energy, and a filter having a stopband and a passband. The filter is coupled to the qubit and to the energy dissipation structure. The stopband includes the first frequency and the passband includes the second frequency for reducing qubit leakage errors.

During normal operation of a processor, voltage droop is likely to occur and there is, therefore, a need for techniques for rapidly addressing this droop so as to reduce the probability of circuit timing failures. This problem is addressed by provided an apparatus that is configured to detect the droop and react to mitigate the droop. The apparatus includes a frequency divider that is configured to receive an output of a clock signal generator (e.g. a phase locked loop) and produce an output signal in which a predefined fraction of the clock pulses in the output of the clock signal generator are removed from the output signal. By reducing the frequency of the clock signal in this way (as may be understood by examining equation 3) V.sub.DD is increased, hence mitigating the voltage droop. This technique provides a fast throttling mechanism that prevents excessive V.sub.DD droop across the processor.

A local oscillator buffer circuit comprises a complementary common-source stage comprising a first p-channel transistor (MCSP) and a first n-channel transistor (MCSN), arranged such that their respective gate terminals are connected together at a first input node, and their respective drain terminals of each of is connected together at a buffer output node. A complementary source-follower stage comprises a second p-channel transistor (MSFP) and a second n-channel transistor (MSFN), arranged such that their respective gate terminals are connected together at a second input node, and their respective source terminals are connected together at the buffer output node.

A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. Input signals in the form of digital signals are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node which provides a majority function of the inputs. The majority node is then coupled driver circuitry which can be any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. In the multi-input majority or minority gates, the non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels. Bringing the majority output close to rail-to-rail voltage eliminates the high leakage problem faced from majority gates formed using linear input capacitors.

In an embodiment, a method includes filtering, with a low-pass filter, a voltage signal (V.sub.dd) of a chip to create a filtered signal (V.sub.ref). The method further includes dividing V.sub.ref by a given factor. The method further includes determining whether a voltage droop occurred in V.sub.dd by comparing V.sub.dd to the divided V.sub.ref. The method further includes outputting a droop detection signal if V.sub.dd is less than the divided V.sub.ref. In an embodiment, dividing V.sub.ref by the given factor includes selecting, with a multiplexer, one of a plurality of divided V.sub.ref signals outputted by a voltage divider. The selecting is based on a selection signal.