Integrated circuits such as application specific integrated circuits or programmable logic devices may include multiple copies of a same circuit together with a majority vote circuit in a configuration that is sometimes also referred to as multi-mode redundancy. An adder circuit may be coupled to these multiple copies and produce a carry-out signal and a sum signal based on signals received from the multiple copies. The carry-out signal of the adder circuit may provide the result of the majority vote operation. A logic exclusive OR gate may perform a logic exclusive OR operation between the sum signal and the carry-out signal, thereby generating an error signal. The error signal may indicate that one of the multiple copies produces an output that is different than the outputs produced by the other copies.

A device for monitoring a critical path of an integrated circuit includes a replica of the critical path formed by sequential elements mutually separated by delay circuits that are programmable though a corresponding main multiplexer. A control circuit controls delay selections made by each main multiplexer. A sequencing module operates to sequence each sequential element using a main clock signal by delivering, in response to a main clock signal, respectively to the sequential elements, secondary clock signals that are mutually time shifted in such a manner as to take into account the propagation time inherent to the main multiplexer.

A circuit arrangement includes two switching group series circuits of switch assemblies, switch-mode power supply units, and two capacitor bridges connecting the switching group series circuits. Each switch assembly has a parallel circuit of a semiconductor switch and a freewheeling diode as well as a driver for actuating the semiconductor switch. Each switch-mode power supply unit is associated with a switch pair of semiconductor switches and supplies the drivers of both semiconductor switches of the switch pair with energy. Each switch pair is formed by a semiconductor switch of a first switching group series circuit and a semiconductor switch of a second switching group series circuit. A power convertor module having the circuit arrangement is also provided.

A field programmable gate array (FPGA) includes a temperature sensor array. The FPGA also includes a supply voltage modulation circuit. The supply voltage modulation circuit is coupled to the temperature sensor array.

An Ultra Low Voltage (ULV) digital circuit includes a logic circuit comprising a plurality of logic gates and a plurality of buffered interconnects for connecting between the plurality of logic gates, a temperature sensor configured to detect a temperature of the logic circuit, and a voltage controller configured to control a driving voltage provided to the logic circuit in order to reduce a power consumption of the logic circuit based on the detected temperature. Each of the plurality of logic gates and buffered interconnects reduces a signal delay as a temperature increases.

An apparatus, comprising a clock adapted to provide a clock signal alternating with a cycle between a first level and a second level if a timing violation is not detected; a first latch adapted to be clocked such that it passes a first signal when the clock signal is at the first level; a second combinational logic adapted to output a second signal based on the first signal passed through the first latch; a second latch adapted to be clocked such that it passes the second signal when the clock signal is at the second level; a detecting means adapted to detect the timing violation of at least one of the first signal and of the second signal; a time stretching means adapted to stretch, if the timing violation is detected, the clock such that the clock alternates between the first level and the second level with a delay.

An apparatus comprising: a sensor; and a resistor array comprising a set of resistors; wherein on a first cycle: at least one first of said resistors is configured to provide a first resistance value; and on a second cycle: at least one second of said resistors is configured to provide said first resistance value.

An in-situ temperature compensation method of an electronic device and an associated temperature sensor includes providing airflow from a vortex air gun to a board including the electronic device and the associated temperature sensor; determining an associated offset at various temperatures in an operating range; and creating and storing a calibration table in memory including the associated offsets at the various temperatures, the calibration table is used during operation of the electronic device for compensation due to temperature variation. A system includes a board, an electronic device disposed to the board; a temperature sensor disposed on the board; a processor disposed to the board and communicatively coupled to the electronic device and the temperature sensor; and instructions that cause the processor to determine an associated offset at various temperatures in an operating range, and create and store a calibration table in memory with the associated offsets at the various temperatures.

Methods and systems for operating a programmable logic fabric including a dynamic parameter scaling controller that tracks an operating parameter that functions at multiple operating conditions by maintaining the operating parameter while cycling through a multiple operating conditions during a calibration mode using the calibration configuration for the programmable logic fabric. The dynamic parameter scaling controller also stores one or more functional values for the operating parameter in a calibration table. The dynamic parameter scaling controller also operates the programmable logic fabric using a design configuration using dynamic values for the operating parameter based at least in part on the one or more operating conditions.

A gate voltage magnitude compensation equalization method and circuit for series operation of power switch transistors are provided. A dynamic voltage equalization of series-connected power switch transistors is implemented by using sampling principles where voltages of the power switch transistors are controlled by gate voltage magnitude and unbalanced voltage differentials are converted into unbalanced current differentials of buffer currents. The gate voltage magnitude compensation equalization method and circuit relates to differential control and works in a dynamic voltage change process of the series-connected power switch transistors, without having a negative effect on operation of the power switch transistors under normal operating conditions. Only adopting passive devices, the gate voltage magnitude compensation equalization circuit has a simple structure, is easy to integrate on a device drive board, implements response tracking of unbalanced voltage and voltage equalization of the series-connected power switch transistors, and improve speedability and stability of voltage equalization control.