The present application discloses a reference voltage circuit with temperature compensation, in which a voltage with a positive temperature coefficient is provided by a current source and an impedance device, and in the meanwhile, a voltage with a negative temperature coefficient is provided by a voltage source. Hereby, the reference voltage circuit according to the invention provides a reference voltage with temperature compensation at an output terminal.

An embodiment level converter circuit is configured to receive, as a current supply, a current proportional to temperature.

An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.

An embodiment level converter circuit is configured to receive, as a current supply, a current proportional to temperature.

This application relates to control of semiconductor devices, in particular MOS devices, so as to reduce RTS/flicker noise. A circuit (100) includes a first MOS device (103, 104) and a bias controller (107). The circuit is operable in at least a first circuit state (P.sub.RO) in which the first MOS device is active to contribute to a first signal (Sout) and a second circuit state (P.sub.RST) in which the first MOS device does not contribute to the first signal. The bias controller is operable to control voltages at one or more terminals of the first MOS device to apply a pre-bias (V.sub.PB1, V.sub.PB2) during an instance of the second circuit state. The pre-bias is applied to set an occupancy state of charge carriers traps within the first MOS device, to limit noise during subsequent operation in the first circuit state. In embodiments, the bias controller is configured so that at least one parameter of the pre-bias is selectively variable in use based on one or more operating conditions.

Embodiments provide for a tunable driving circuit by monitoring a frequency of a ring oscillator of an electrical integrated circuit connected to an optical modulator to determine operational characteristics of the electrical integrated circuit; setting, based on the operational characteristics, a driving voltage for a plurality of tunable inverters and a plurality of fixed gain inverters that control the optical modulator, wherein each tunable inverter of the plurality of tunable inverters is connected in parallel with a corresponding fixed gain inverter of the plurality of fixed gain inverters on one of a first arm and a second arm connected to the optical modulator; and setting an amplification strength for the plurality of tunable inverters based on the operational characteristics.

A gate voltage magnitude compensation equalization method and circuit for series operation of power switch transistors are provided. A dynamic voltage equalization of series-connected power switch transistors is implemented by using sampling principles where voltages of the power switch transistors are controlled by gate voltage magnitude and unbalanced voltage differentials are converted into unbalanced current differentials of buffer currents. The gate voltage magnitude compensation equalization method and circuit relates to differential control and works in a dynamic voltage change process of the series-connected power switch transistors, without having a negative effect on operation of the power switch transistors under normal operating conditions. Only adopting passive devices, the gate voltage magnitude compensation equalization circuit has a simple structure, is easy to integrate on a device drive board, implements response tracking of unbalanced voltage and voltage equalization of the series-connected power switch transistors, and improve speedability and stability of voltage equalization control.

During normal operation of a processor, voltage droop is likely to occur and there is, therefore, a need for techniques for rapidly addressing this droop so as to reduce the probability of circuit timing failures. This problem is addressed by provided an apparatus that is configured to detect the droop and react to mitigate the droop. The apparatus includes a frequency divider that is configured to receive an output of a clock signal generator (e.g. a phase locked loop) and produce an output signal in which a predefined fraction of the clock pulses in the output of the clock signal generator are removed from the output signal. By reducing the frequency of the clock signal in this way (as may be understood by examining equation 3) V.sub.DD is increased, hence mitigating the voltage droop. This technique provides a fast throttling mechanism that prevents excessive V.sub.DD droop across the processor.

A buffer apparatus, a chip and an electronic device. The apparatus comprises: a voltage adjustment module (10) comprising a first P-type metal-oxide-semiconductor field-effect transistor (PMOS), wherein the voltage adjustment module (10) is used for receiving an input voltage, using a threshold voltage for the first PMOS to adjust the input voltage, and outputting a driving voltage; and a buffer module (20) electrically connected to the voltage adjustment module (10) and used for receiving an input signal, buffering the input signal under the driving voltage, and outputting a buffered signal. The driving voltage obtained by using the threshold voltage for the first PMOS to adjust the input voltage can compensate for a process corner of the buffer module (20), such that the range of a flip point voltage of the buffer module (20) becomes small and meets process requirements.

Embodiments provide for a tunable driving circuit by monitoring a frequency of a ring oscillator of an electrical integrated circuit connected to an optical modulator to determine operational characteristics of the electrical integrated circuit; setting, based on the operational characteristics, a driving voltage for a plurality of tunable inverters and a plurality of fixed gain inverters that control the optical modulator, wherein each tunable inverter of the plurality of tunable inverters is connected in parallel with a corresponding fixed gain inverter of the plurality of fixed gain inverters on one of a first arm and a second arm connected to the optical modulator; and setting an amplification strength for the plurality of tunable inverters based on the operational characteristics.