An interconnection network for providing data transfer between a plurality of nodes of an integrated circuit comprises a number of endpoints for exchanging data with respective nodes of the integrated circuit, a primary network to route a primary payload from a source endpoint to a destination endpoint; and a redundant network to route, to the destination endpoint, a redundant payload comprising a first check code calculated based on at least a portion of the primary payload, the first check code having fewer bits than said at least a portion of the primary payload. The destination endpoint comprises error checking circuitry to perform an error checking operation to calculate a second check code based on the primary payload received via the primary network, and verify integrity of the primary payload based on a comparison of the second check code with the first check code received via the redundant network.

An apparatus and method for transmitting signals between two clock domains in which at least one of a phase and a frequency of clock signals in the two clock domains is misaligned. The apparatus includes a first primary interface and a first redundant interface in the first clock domain for receiving a primary signal and a first checking signal respectively, and a second primary interface and second redundant interface in the second clock domain for outputting the primary signal and a second redundant signal respectively. The primary signal and the checking signals are separated by a predetermined time delay and the second checking signal is generated in the second clock domain based on the primary signal. Checking circuitry is provided in the second clock domain to perform an error checking procedure based on the two checking signals and to provide the second checking signal to the second redundant interface.

Disclosed herein is a circuit including first and second input circuits. The first input circuit is configured to receive first and second logic signals and to source current to first and second control nodes if at least one of the first and second logic signals is at a logic low. The second input circuit is configured to receive the first and second logic signals and to sink current from the first and second control nodes if at least one of the first and second logic signals is at a logic high. A first output circuit is configured to source current to an output node when current is sunk from the first control node. A second output circuit is configured to sink current from the output node when current is sourced to the second control node. A latch is coupled to the output node.

A power distributor, in particular for an on-board network of a motor vehicle, has an intermediate tap, two power outputs, and one each switching unit for each power output. A switch is provided for a need-based blocking of the associated power output. Each of the switching units is designed in such a way that a blocking of the associated power output takes place, if, in the event a voltage drop at the associated power output and/or at the intermediate tap below a first setpoint value, an error case is determined. The greater the corresponding voltage drop, the faster the blocking of the associated power output takes place.

A processing system includes a timer circuit and a processing circuit. The timer circuit is configured to generate a system time signal. The processing circuit is configured to receive the system time signal, detect whether the system time signal reaches or exceeds a given reference value, and start execution of a given processing operation in response to the detection. The timer circuit has associated an error code calculation circuit configured to compute a first set of error detection bits as a function of bits of the system time signal. The processing circuit has an associated error detection circuit configured to: compute a second set of error detection bits as a function of the bits of the system time signal received, compare the first set of error detection bits with the second set of error detection bits, and generate an error signal in response to the comparison.

A power distributor, in particular for an on-board network of a motor vehicle, has an intermediate tap, two power outputs, and one each switching unit for each power output. A switch is provided for a need-based blocking of the associated power output. Each of the switching units is designed in such a way that a blocking of the associated power output takes place, if, in the event a voltage drop at the associated power output and/or at the intermediate tap below a first setpoint value, an error case is determined. The greater the corresponding voltage drop, the faster the blocking of the associated power output takes place.

A relay apparatus comprises input ports, output ports, and first and second relays. The first relay comprises: a first contact group comprising n?2 first contacts arranged in parallel and moveable between open and closed positions by a first common armature; and a second contact group comprising n second contacts arranged in parallel and movable between open and closed positions by a second common armature, wherein the first and second contacts are arranged in series in pairs. The second relay includes m<n contacts arranged in parallel and moveable between open and closed positions by a third common armature. The first and second relays are arranged in series between the input and output ports such that the relay apparatus has plural parallel switching paths. A contact of the second relay is arranged in series with a first contact of the first contact group in m switching paths.

A semiconductor device according to an aspect of the present disclosure includes: a plurality of line layers; a first line; and a second line that is not connected to the first line and is redundantly provided to transfer a signal having a level same as a level of a signal transferred through the first line. The first line and the second line are included in different layers out of the plurality of line layers, and a distance between the first line and the second line is longer than an interlayer distance between line layers next to each other out of the plurality of line layers.

An apparatus and method for transmitting signals between two clock domains in which at least one of a phase and a frequency of clock signals in the two clock domains is misaligned. The apparatus includes a first primary interface and a first redundant interface in the first clock domain for receiving a primary signal and a first checking signal respectively, and a second primary interface and second redundant interface in the second clock domain for outputting the primary signal and a second redundant signal respectively. The primary signal and the checking signals are separated by a predetermined time delay and the second checking signal is generated in the second clock domain based on the primary signal. Checking circuitry is provided in the second clock domain to perform an error checking procedure based on the two checking signals and to provide the second checking signal to the second redundant interface.

An interconnection network for providing data transfer between a plurality of nodes of an integrated circuit comprises a number of endpoints for exchanging data with respective nodes of the integrated circuit, a primary network to route a primary payload from a source endpoint to a destination endpoint; and a redundant network to route, to the destination endpoint, a redundant payload comprising a first check code calculated based on at least a portion of the primary payload, the first check code having fewer bits than said at least a portion of the primary payload. The destination endpoint comprises error checking circuitry to perform an error checking operation to calculate a second check code based on the primary payload received via the primary network, and verify integrity of the primary payload based on a comparison of the second check code with the first check code received via the redundant network.