A memory device and an operation method thereof are provided. The operation method includes: in a first phase, selecting a global signal line, selecting a first string select line, unselecting a second string select line, selecting a first word line, and unselecting a second word line; sensing during a second phase; in a third phase, keeping voltages of the global signal line, the selected first word line and the unselected second word line, unselecting the first string select line and selecting the second string select line to switch voltages of the first and the second string select lines; and sensing during a fourth phase.

A positive-logic FET switch stack that does not require a negative bias voltage, and which can withstand application of a high voltage RF signal without requiring terminal capacitors. Some embodiments include a stack of FET switches, with at least one FET requiring a negative V.sub.GS to turn OFF and configured so as to not require a negative voltage, series-coupled on at least one end to an end-cap FET that turns OFF when the V.sub.GS of such end-cap FET is essentially zero volts, wherein at least one end-cap FET is configured to be coupled to a corresponding RF signal source and has a gate coupled to the corresponding RF signal source through an associated switch circuit. The switch circuit may include an NMOSFET and a PMOSFET, or a diode and an NMOSFET, or a diode and an NMOSFET and a PMOSFET.

A positive-logic FET switch stack that does not require a negative bias voltage, and which can withstand application of a high voltage RF signal without requiring terminal capacitors. Some embodiments include a stack of FET switches, with at least one FET requiring a negative V.sub.GS to turn OFF and configured so as to not require a negative voltage, series-coupled on at least one end to an end-cap FET that turns OFF when the V.sub.GS of such end-cap FET is essentially zero volts, wherein at least one end-cap FET is configured to be coupled to a corresponding RF signal source and has a gate coupled to the corresponding RF signal source through an associated switch circuit. The switch circuit may include an NMOSFET and a PMOSFET, or a diode and an NMOSFET, or a diode and an NMOSFET and a PMOSFET.

Provided is a method and an apparatus for optimizing memory power and provide a method and an apparatus for optimizing memory power by minimizing power consumed by pins of a memory by using an SBR pattern. The method of optimizing memory power using a PAM-4 (Pulse-Amplitude Modulation-4) method includes: setting a ratio and sizes of a pull-up transistor and a pull-down transistor included in a driver according to a smallest size of a plurality of eyes included in an eye diagram of a memory; and setting a reference voltage of a sampler and a phase interpolator (PI) digital code value included in the memory by using a signal bit response (SBR) pattern.

A non-volatile memory device, including a non-volatile memory cell array, a sense amplifier, a random access memory (RAM), and a buffer circuit, is provided. The sense amplifier is configured to generate readout data. The RAM is configured to store write-in data. The buffer circuit generates a detection result according to target data and the readout data, and writes the detection result to the RAM.

An off chip driver circuit includes a pull-up circuit and a pull-down circuit. The pull-up circuit includes several first transistors and a first resistance circuit coupled between the first transistors and a input/output pad. The first transistors generate a first voltage to the first resistance circuit. The first resistance circuit transmits, in response to a first control signal, the first voltage to the input/output pad and to have a variable resistance according to the first control signal. The pull-down circuit includes several second transistors and a second resistance circuit coupled between the second transistors and the input/output pad. The second transistors generate a second voltage to the second resistance circuit. The second resistance circuit transmits, in response to a second control signal, the second voltage to the input/output pad and to have a variable resistance according to the second control signal.

A negative voltage level conversion control circuit comprises a negative voltage generation circuit, a bias circuit, and a level shift unit circuit, wherein an output end of the bias circuit is connected to the level shift unit circuit, and the other end of the bias circuit is connected to the negative voltage generation circuit; an output end of the negative voltage generation circuit is connected to the level shift unit circuit; the bias circuit is configured to receive an enable signal and output a bias voltage; the bias voltage is used for controlling a switching process of the level shift unit circuit; the enable signal is used for enabling the bias circuit and the negative voltage generation circuit.

A negative voltage level conversion control circuit comprises a negative voltage generation circuit, a bias circuit, and a level shift unit circuit, wherein an output end of the bias circuit is connected to the level shift unit circuit, and the other end of the bias circuit is connected to the negative voltage generation circuit; an output end of the negative voltage generation circuit is connected to the level shift unit circuit; the bias circuit is configured to receive an enable signal and output a bias voltage; the bias voltage is used for controlling a switching process of the level shift unit circuit; the enable signal is used for enabling the bias circuit and the negative voltage generation circuit.

An apparatus, a memory device, and a method for storing parameter codes with respect to asymmetric on-die-termination (ODT) are provided. The apparatus is connected to an external device via a signal line, and includes: an on-die termination (ODT) circuit set in a first ODT state; a plurality of signal pins, each of which is connected to the signal line; and an ODT control circuit configured to: identify whether a second ODT state of the external device corresponds to the first ODT state, and based on the apparatus being an asymmetric ODT in which the first ODT state and the second ODT state are different, provide an asymmetric ODT parameter code to the external device, and disable the ODT circuit when a signal is not transmitted through the signal line.

A system and method for monitoring a code overwrite error of a Redriver chip are disclosed. An analog to digital converter (ADC) monitors whether an EEPROM code of a Redriver chip has been overwritten in error. A Switch chip is utilized to separate the Redriver chip from a system management bus (SMbus) controller. A pull-up resistor keeps an SMbus at a Redriver chip/EEPROM side in a pull-up state. The ADC is utilized to monitor the SMbus. When an abnormal low level is monitored, an alarm signal is sent to the SMbus controller to give a risk alarm for an overwrite error. In addition, according to different ADC sampling rates, an SMbus may also be connected between the SMbus controller and an ADC with a high sampling rate, whereby SMbus data can be monitored.