According to an aspect, a current mode logic circuit comprise a first transistor to which an input voltage is applied, a second transistor connected in parallel with the first transistor; and a voltage sampling circuit which is connected to the first transistor and the second transistor and resets an output voltage output by integrating the input voltage for a predetermined set time (T) in a manner in which the output voltage is integrated in a direction opposite to a direction in which the input voltage is integrated for the predetermined set time (T).

A size setting method for a power switch transistor and a system thereof are proposed. A load current extracting step is performed to extract a first load current and a second load current. A limited voltage drop calculating step is performed to calculate a limited voltage drop according to a speed proportional value, the first load current and the second load current. A standard supply current calculating step is performed to calculate a standard supply current according to the limited voltage drop. A simulated supply current calculating step is performed to calculate a simulated supply current according to the standard supply current, the limited voltage drop and a line voltage value. A size setting step is performed to compare the first load current with the simulated supply current to calculate a size parameter, and set a size of the power switch transistor according to the size parameter.

A size setting method for a power switch transistor and a system thereof are proposed. A load current extracting step is performed to extract a first load current and a second load current. A limited voltage drop calculating step is performed to calculate a limited voltage drop according to a speed proportional value, the first load current and the second load current. A standard supply current calculating step is performed to calculate a standard supply current according to the limited voltage drop. A simulated supply current calculating step is performed to calculate a simulated supply current according to the standard supply current, the limited voltage drop and a line voltage value. A size setting step is performed to compare the first load current with the simulated supply current to calculate a size parameter, and set a size of the power switch transistor according to the size parameter.

A memory device is provided. The memory device includes a bit cell having a first invertor connected between a first node and a second node and a second invertor connected between the first node and the second node. The first invertor and the second invertor are cross coupled at a first data node and a second data node. The memory device further includes a pull down circuit connected to the second node. The pull down circuit is operative to pull down a voltage of the second node below a ground voltage in response to an enable signal.

A method, implemented in a serializer for quarter rate serialization, is disclosed. The method includes receiving a plurality of in-phase and quarter-phase clock signals defining a quarter phase clock. The method includes receiving a quarter rate data input and sequentially outputting data in accordance with the quarter phase clock. The method includes receiving at least one data input from amongst the quarter rate input and outputting a first logical output in accordance with the in-phase clock signal and the quarter-phase clock signal. The method includes receiving said at least one data input and outputting a second logical output in accordance a complementary in-phase clock signal and a complementary quarter-phase clock signal. The method includes outputting, an output associated with the branch.

Disclosed herein is an apparatus that includes a first wiring layer including first and second conductive patterns extending in a second direction and coupled to source and drain regions, respectively, and a second wiring layer including third and fourth conductive patterns extending in the second direction and coupled to the first and second conductive patterns, respectively. The first conductive pattern has first and second sections arranged in the second direction, and the second conductive pattern has third and fourth sections arranged in the second direction. The first and fourth sections are arranged in a first direction, and the second and third sections are arranged in the first direction. The third conductive pattern covers the first section without covering the second section. The fourth conductive pattern covers the third section without covering the fourth section.

A temperature measurement circuit includes a band-gap reference circuit configured to generate a band-gap reference voltage that is fixed regardless of an operation temperature, a reference voltage generator circuit configured to generate a measurement reference voltage by adjusting the band-gap reference voltage, a sensing circuit configured to generate a temperature-variant voltage based on a bias current, where the temperature-variant voltage is varied depending on the operation temperature, an analog-digital converter circuit configured to generate a first digital code indicating the operation temperature based on the measurement reference voltage and the temperature-variant voltage, and an analog built-in self-test (BIST) circuit configured to generate a plurality of flag signals indicating whether each of the band-gap reference voltage, the measurement reference voltage, and a bias voltage corresponding to the bias current is included in a predetermined range.

A semiconductor device may include a division control circuit and a latch circuit. The division control circuit may be configured to divide an external clock to generate a first preliminary divided clock and a second preliminary divided clock. The division control circuit may be configured to output the first and second preliminary divided clocks or any one of the first and second preliminary divided clocks as first and second divided clocks. The latch circuit may be configured to latch an external control signal in response to the first and second divided clocks and configured to output latched signals as first and second latch control signals.

The disclosure provides a level shifter circuit. The level shifter circuit includes a first transistor and a second transistor. The first transistor and the second transistor generate an output voltage according to a first control signal and a second control signal, respectively. A time interval of rising edges of the output voltage is greater than a time interval of falling edges of the output voltage.

A 3D field programmable gate array (FPGA) system, and method of manufacture therefor, includes: a field programmable gate array (FPGA) die having a configurable power on reset (POR) unit; a heterogeneous integrated circuit die coupled to the FPGA die; and a 3D power on reset (POR) output configured by the configurable POR unit for initializing the FPGA die and the heterogeneous integrated circuit die.