Disclosed is an electromagnetic-circuit co-design approach for massively reconfigurable, multifunctional, and high-speed programmable metasurfaces with integrated chip tiling. The ability to manipulate the incident electromagnetic fields in a dynamically programmable manner and at high speeds using integrated chip tiling approach is also disclosed. The scalable architecture uses electromagnetic-circuit co-design of metasurfaces where each individual subwavelength meta-element is uniquely addressable and programmable. The disclosed device comprises a large array of such meta-elements. The design relies on integrated high frequency switches designed in conjugation with meta-element for massive reconfigurability of incident amplitude and phase. The disclosed chip is multi-functional and can perform beamforming, high speed spatial light modulation, dynamic holographic projections, and wavefront manipulation.

The present invention relates to a kind of magnetic heterojunction structure and the method of controlling and achieving spin logic and multiple-state storage functions. The said single magnetic heterojunction structure comprises the substrate, in-plane anti-ferromagnetic layer, in-plane ferromagnetic layer, nonmagnetic layer, vertical ferromagnetic layer, and vertical anti-ferromagnetic layer respectively from the bottom up; the said in-plane ferromagnetic layer and the said vertical ferromagnetic layer are coupled together through the said nonmagnetic layer in the middle; in-plane exchange biases, namely exchange biases in the plane, exist between the said in-plane ferromagnetic layer and the said in-plane anti-ferromagnetic layer, and out-of-plane exchange biases, namely exchange biases out of the plane, exist between the said vertical ferromagnetic layer and the said vertical anti-ferromagnetic layer.

The present invention relates to a kind of magnetic heterojunction structure and the method of controlling and achieving spin logic and multiple-state storage functions. The said single magnetic heterojunction structure comprises the substrate, in-plane anti-ferromagnetic layer, in-plane ferromagnetic layer, nonmagnetic layer, vertical ferromagnetic layer, and vertical anti-ferromagnetic layer respectively from the bottom up; the said in-plane ferromagnetic layer and the said vertical ferromagnetic layer are coupled together through the said nonmagnetic layer in the middle; in-plane exchange biases, namely exchange biases in the plane, exist between the said in-plane ferromagnetic layer and the said in-plane anti-ferromagnetic layer, and out-of-plane exchange biases, namely exchange biases out of the plane, exist between the said vertical ferromagnetic layer and the said vertical anti-ferromagnetic layer.

A computing device including a logic track including two logic-track magnetic domains separated by a logic-track domain wall, an input track arranged crossing the logic track at a first position of the logic track, and an output track arranged crossing the logic track at a second position of the logic track near the logic-track domain wall. The input track includes at least one input-track magnetic domain, and each of the at least one input-track magnetic domain includes at least one input-track storage unit configured to store binary 0 or 1. The output track includes at least one output-track magnetic domain, and each of the at least one output-track magnetic domain includes at least one output-track storage unit configured to store binary 0 or 1.

Synthesizing a control object for a computing event, the control object for securing a computing resource based on a set of access and privilege information provided through a set of mediated associations that are represented by an enchained set of certificates, portions of which are encrypted including entity-specific paths to entity-specific predecessor certificates and partial decryption keys therefor, wherein the control object is applied to secure the computing resource for performing a computing action indicated by a process-type entity identified in the certificate for the control object.

A spin transistor memory according to an embodiment includes: a first semiconductor region, a second semiconductor region, and a third semiconductor region, each being of a first conductivity type and disposed in a semiconductor layer; a first gate disposed above the semiconductor layer between the first semiconductor region and the second semiconductor region; a second gate disposed above the semiconductor layer between the second semiconductor region and the third semiconductor region; and a first ferromagnetic layer, a second ferromagnetic layer, and a third ferromagnetic layer disposed on the first semiconductor region, the second semiconductor region, and the third semiconductor region respectively.

A spin transistor memory according to an embodiment includes: a first semiconductor region, a second semiconductor region, and a third semiconductor region, each being of a first conductivity type and disposed in a semiconductor layer; a first gate disposed above the semiconductor layer between the first semiconductor region and the second semiconductor region; a second gate disposed above the semiconductor layer between the second semiconductor region and the third semiconductor region; and a first ferromagnetic layer, a second ferromagnetic layer, and a third ferromagnetic layer disposed on the first semiconductor region, the second semiconductor region, and the third semiconductor region respectively.

A magnetic field controlled transistor circuit includes a first electrode, a second electrode, and a channel including a magneto-resistive material. The channel is arranged between the first and second electrodes and electrically coupled to the first and second electrodes. The transistor circuit further includes a third electrode, a fourth electrode, and a control layer including an electrically conductive material. The control layer is arranged between the third and fourth electrodes and electrically coupled to the third and fourth electrodes. In addition, an insulating layer including an insulating material is provided. The insulating layer is arranged between the channel and the control layer and configured to electrically insulate the channel from the control layer. A related method for operating a transistor circuit and a corresponding design structure are also provided.

A magnetic field controlled transistor circuit includes a first electrode, a second electrode, and a channel including a magneto-resistive material. The channel is arranged between the first and second electrodes and electrically coupled to the first and second electrodes. The transistor circuit further includes a third electrode, a fourth electrode, and a control layer including an electrically conductive material. The control layer is arranged between the third and fourth electrodes and electrically coupled to the third and fourth electrodes. In addition, an insulating layer including an insulating material is provided. The insulating layer is arranged between the channel and the control layer and configured to electrically insulate the channel from the control layer. A related method for operating a transistor circuit and a corresponding design structure are also provided.

Described is an interconnect which comprises: a first end having a ferromagnetic layer coupled to a first magnetoelectric material layer; and a second end having a second magnetoelectric material layer coupled to the ferromagnetic layer, wherein the ferromagnetic layer extends from the first end to the second end. Described is a majority gate device which comprises: a ferromagnetic layer; and first, second, third, and fourth magnetoelectric material layers coupled to the ferromagnetic layer. Described is an apparatus which comprises: a first end having a ferromagnetic layer coupled to a first magnetoelectric material layer; and a second end having a tunnel junction device coupled to the ferromagnetic layer. Described is an apparatus which comprises: a first terminal coupled to a tunneling junction device; a second terminal coupled to a layer coupling the tunneling junction device and a magnetoelectric device; and a third terminal coupled to the magnetoelectric device.