A cryogenic memory cell and a memory device are provided. The cryogenic memory cell includes a spin moment transfer device. The spin moment transfer device converts a write current into a spin polarization current and changes a magnetic polarization direction under the action of the spin polarization current to achieve write storage of 0 and 1. The cryogenic memory cell also includes a nano-superconducting quantum interference device; a ground terminal of the nano-superconducting quantum interference device is in common-ground connection with a ground terminal of the spin moment transfer device, and the nano-superconducting quantum interference device undergoes a magnetic flux change under the action of a change in the magnetic polarization direction of the spin moment transfer device, thereby switching between a superconducting state and a non-superconducting state under a read current bias, to achieve read-out of 0 and 1.

A system comprises pulse program compiler circuitry operable to analyze a pulse program that includes a pulse operation statement, and to generate, based on the pulse program, machine code that, if loaded into a pulse generation and measurement circuit, configures the pulse generation and measurement circuit to generate one or more pulses and/or process one or more received pulses. The pulse operation statement may specify a first pulse to be generated, and a target of the first pulse. The pulse operation statement may specify parameters to be used for processing of a return signal resulting from transmission of the first pulse. The pulse operation statement may specify an expression to be used for processing of the first pulse by the pulse generation and measurement circuit before the pulse generation and measurement circuit sends the first pulse to the target.

A system comprises pulse program compiler circuitry operable to analyze a pulse program that includes a pulse operation statement, and to generate, based on the pulse program, machine code that, if loaded into a pulse generation and measurement circuit, configures the pulse generation and measurement circuit to generate one or more pulses and/or process one or more received pulses. The pulse operation statement may specify a first pulse to be generated, and a target of the first pulse. The pulse operation statement may specify parameters to be used for processing of a return signal resulting from transmission of the first pulse. The pulse operation statement may specify an expression to be used for processing of the first pulse by the pulse generation and measurement circuit before the pulse generation and measurement circuit sends the first pulse to the target.

A system comprises pulse program compiler circuitry operable to analyze a pulse program that includes a pulse operation statement, and to generate, based on the pulse program, machine code that, if loaded into a pulse generation and measurement circuit, configures the pulse generation and measurement circuit to generate one or more pulses and/or process one or more received pulses. The pulse operation statement may specify a first pulse to be generated, and a target of the first pulse. The pulse operation statement may specify parameters to be used for processing of a return signal resulting from transmission of the first pulse. The pulse operation statement may specify an expression to be used for processing of the first pulse by the pulse generation and measurement circuit before the pulse generation and measurement circuit sends the first pulse to the target.

A system comprises pulse program compiler circuitry operable to analyze a pulse program that includes a pulse operation statement, and to generate, based on the pulse program, machine code that, if loaded into a pulse generation and measurement circuit, configures the pulse generation and measurement circuit to generate one or more pulses and/or process one or more received pulses. The pulse operation statement may specify a first pulse to be generated, and a target of the first pulse. The pulse operation statement may specify parameters to be used for processing of a return signal resulting from transmission of the first pulse. The pulse operation statement may specify an expression to be used for processing of the first pulse by the pulse generation and measurement circuit before the pulse generation and measurement circuit sends the first pulse to the target.

The present disclosure relates to a compiling method (50) for converting an input quantum circuit into an output quantum circuit compliant with predetermined constraints of a quantum computer, said input quantum circuit being composed of quantum gates to be applied to a set of qubits, said quantum gates arranged successively in an execution order, wherein said method comprises, for each quantum gate of the input quantum circuit processed according to the execution order: if the processed quantum gate corresponds to an operator of a set of synthesizable operators: (S53) update the synthesizable accumulated operator to include the operator corresponding to the quantum gate, otherwise: a) (S54) synthesize a partial quantum sub-circuit partially implementing the current synthesizable accumulated operator and modify accordingly the synthesizable accumulated operator, and b) (S55) append the partial quantum sub-circuit to the output quantum circuit.

The present disclosure relates to a compiling method (50) for converting an input quantum circuit into an output quantum circuit compliant with predetermined constraints of a quantum computer, said input quantum circuit being composed of quantum gates to be applied to a set of qubits, said quantum gates arranged successively in an execution order, wherein said method comprises, for each quantum gate of the input quantum circuit processed according to the execution order: if the processed quantum gate corresponds to an operator of a set of synthesizable operators: (S53) update the synthesizable accumulated operator to include the operator corresponding to the quantum gate, otherwise: a) (S54) synthesize a partial quantum sub-circuit partially implementing the current synthesizable accumulated operator and modify accordingly the synthesizable accumulated operator, and b) (S55) append the partial quantum sub-circuit to the output quantum circuit.

A method is provided. The method includes determining a corresponding relationship between a pulse enveloping parameter and a single pulse duration, and determining a parameter to be optimized; and determining a maximum pulse number, an initialized current pulse number and a preset error tolerance. The method further includes executing an iterative operation including determining a quantum gate matrix to be implemented and a value of a loss function based on the current pulse number and the parameter to be optimized; adjusting a group of parameter values of the parameter to be optimized to minimize the value of the loss function; determining an error with a target quantum gate matrix after the value of the loss function is minimized; and in response to that the current pulse number is less than the maximum pulse number and the error is greater than the error tolerance, adding one to the current pulse number.

A method is provided. The method includes determining a corresponding relationship between a pulse enveloping parameter and a single pulse duration, and determining a parameter to be optimized; and determining a maximum pulse number, an initialized current pulse number and a preset error tolerance. The method further includes executing an iterative operation including determining a quantum gate matrix to be implemented and a value of a loss function based on the current pulse number and the parameter to be optimized; adjusting a group of parameter values of the parameter to be optimized to minimize the value of the loss function; determining an error with a target quantum gate matrix after the value of the loss function is minimized; and in response to that the current pulse number is less than the maximum pulse number and the error is greater than the error tolerance, adding one to the current pulse number.

A system and method comprising a cryogenic adiabatic circuit in a cryogenic environment and a clock generator at a higher temperature, the circuit's clock lines can be connected across the temperature gradient to the clock generator, where the clock generator runs below the frequency that would yield power dissipation equal to the static dissipation of a functionally equivalent CMOS circuit at room temperature, resulting in lower power for the function than possible at room temperature irrespective of the speed of operation.