A physical quantity measurement apparatus includes a first resonator, a second oscillator, and an integrated circuit device. The integrated circuit device includes a first oscillation circuit that causes the first resonator to oscillate, and thus generate a first clock signal having a first clock frequency, a second oscillation circuit that causes the second oscillator to oscillate, and thus generate a second clock signal having a second clock frequency which is different from the first clock frequency, and a measurement unit that is provided with a time-to-digital conversion circuit which converts time into a digital value by using the first clock signal and the second clock signal.

A device with a first MEMS device and a second MEMS device is disclosed. The first MEMS device is configured to sense at least one external influence. The second MEMS device is responsive to the at least one external influence. The first MEMS device is configured to change a state when the at least one external influence exceeds a threshold value. The first MEMS device is configured to retain the state below the threshold value, wherein the change in state of the first MEMS device is done passively and wherein the state of the first MEMS device is indicative of a status of the second MEMS device. In one example, the first MEMS device further comprises a normally open switch that closes when the external influence exceeds the threshold value.

An injection locked frequency divider includes: a resonator circuit including first to fourth inductors; and a mixer circuit receiving an input signal with an input frequency. Each of the third and fourth inductors is coupled between a respective one of the first and second inductors and the mixer circuit. The two circuits cooperate to form a tank circuit having a free-running frequency and defining a frequency locking range which is around three times the free-running frequency and within which the input frequency falls. By at least performing mixing with a differential reference signal pair, the mixer circuit generates, based on the input signal, a differential mixed signal pair with a frequency that is one-third the input frequency.

A circuit includes a random oscillation number generator (RONG) configured to generate first and second pulse signals at first and second RONG outputs. A first counter is coupled to the first RONG output and generates a first count at a first counter output. A second counter is coupled to the second RONG output and generates a second count at a second counter output. A selection circuit is coupled to the first and second counter outputs and to the first and second RONG outputs. A first pulse shaper is connected between the first RONG output and the first counter, and a second pulse shaper is connected between the second RONG output and the second counter.

A device with a first MEMS device and a second MEMS device is disclosed. The first MEMS device is configured to sense at least one external influence. The second MEMS device is responsive to the at least one external influence. The first MEMS device is configured to change a state when the at least one external influence exceeds a threshold value. The first MEMS device is configured to retain the state below the threshold value, wherein the change in state of the first MEMS device is done passively and wherein the state of the first MEMS device is indicative of a status of the second MEMS device. In one example, the first MEMS device further comprises a normally open switch that closes when the external influence exceeds the threshold value.

A frequency divider is provided that includes a plurality of latches for dividing an input clock according to an integer frequency divisor N of three or greater. Each latch is coupled to a corresponding pair of logic gates. For each latch, one of the logic gates in the corresponding pair controls a setting of the latch whereas a remaining one of the logic gates in the corresponding pair controls a resetting of the latch. Each latch outputs a pair of overlapping clock signals that are divided in frequency with respect to the input clock and have a 50% duty cycle. Each logic gate processes a pair of the overlapping clock signal and the input clock signal to provide a non-overlapping clock signal of the same frequency of the overlapping clock signals but have a (50/N) % duty cycle.

A frequency divider is provided that includes a plurality of latches for dividing an input clock according to an integer frequency divisor N of three or greater. Each latch is coupled to a corresponding pair of logic gates. For each latch, one of the logic gates in the corresponding pair controls a setting of the latch whereas a remaining one of the logic gates in the corresponding pair controls a resetting of the latch. Each latch outputs a pair of overlapping clock signals that are divided in frequency with respect to the input clock and have a 50% duty cycle. Each logic gate processes a pair of the overlapping clock signal and the input clock signal to provide a non-overlapping clock signal of the same frequency of the overlapping clock signals but have a (50/N) % duty cycle.

An improved reference current generator for use in an integrated circuit. A voltage difference generator generates two voltages that are separated by a relatively small electrical potential. The two closely separated voltages are applied across a resistive element with relatively large impedance value resulting in a small and stable reference current. The stable reference current is mirrored and, if desired, amplified for use on the integrated circuit. A driver selectively drives state information off chip for assisting in post-silicon correction of unwanted sensitivities. A configuration memory stores values used to adjust effective device widths and lengths for correcting unwanted sensitivities.

Aspects of the disclosure are directed to multi-module frequency division. As may be implemented in accordance with one or more embodiments herein, an apparatus includes latching circuitry having three or fewer vertically-stacked transistors between power rails, which operate to provide output signals from input signals, the output signals having a frequency that is a divided representation of the frequency of the input signals. A pulse widening circuit modifies the output signals by widening a pulse thereof, providing a modified output signal. A further latching circuit may be utilized to perform a further frequency division of the modified output signal. The respective latching circuitry can be used to selectively provide frequency-divided output signals from input signals at respective divided frequencies.

The present technology relates to a signal processing apparatus and method capable of increasing a harmonic rejection ratio while suppressing an increase in power consumption. In one aspect of the present technology, two local signals having a 1/3 duty ratio and phases mutually shifted by a 1/2 period are mixed with each signal of a differential signal, and a difference between results of the mixing of the two local signals is calculated. The present technology can be applied to, for example, a signal processing apparatus, a transmission apparatus, a reception apparatus, a communication apparatus, an electronic apparatus having a transmission function, a reception function, or a communication function, or a computer that controls those apparatuses.