A device with a first MEMS device and a second MEMS device is disclosed. The first MEMS device is configured to sense at least one external influence. The second MEMS device is responsive to the at least one external influence. The first MEMS device is configured to change a state when the at least one external influence exceeds a threshold value. The first MEMS device is configured to retain the state below the threshold value, wherein the change in state of the first MEMS device is done passively and wherein the state of the first MEMS device is indicative of a status of the second MEMS device.

An assembly including a carrier substrate and at least one group of interconnected integrated circuit modules mounted thereon is disclosed. The modules are provided with a connection for transmitting a clock signal through the group of interconnected modules. The modules are also provided with digital input ports and output ports and a logic circuit configured for identifying the position of the modules in the group on the basis of a count of the clock pulses, and on the basis of the logic state of the input and output ports. In one aspect, a method involves the transfer of a token in the form of one or more logic states, through the group of modules, from a first module to a last module, resulting in the identification of all modules in a progressive manner.

A circuit includes a random oscillation number generator (RONG) configured to generate first and second pulse signals at first and second RONG outputs. A first counter is coupled to the first RONG output and generates a first count at a first counter output. A second counter is coupled to the second RONG output and generates a second count at a second counter output. A selection circuit is coupled to the first and second counter outputs and to the first and second RONG outputs. A first pulse shaper is connected between the first RONG output and the first counter, and a second pulse shaper is connected between the second RONG output and the second counter.

An assembly including a carrier substrate and at least one group of interconnected integrated circuit modules mounted thereon is disclosed. The modules are provided with a connection for transmitting a clock signal through the group of interconnected modules. The modules are also provided with digital input ports and output ports and a logic circuit configured for identifying the position of the modules in the group on the basis of a count of the clock pulses, and on the basis of the logic state of the input and output ports. In one aspect, a method involves the transfer of a token in the form of one or more logic states, through the group of modules, from a first module to a last module, resulting in the identification of all modules in a progressive manner.

An integrated circuit (IC) device includes a first IC chip, a second IC chip, and a chip-to-chip interface connected between the first IC chip and the second IC chip. The chip-to-chip interface communicates an interface clock signal and a logic clock signal between the first IC chip and the second IC chip. The interface clock signal is synchronous with a data signal received by one of the first IC chip and the second IC chip. The logic clock signal is asynchronous with the data signal.

A pulse counting circuit receives pulses supplied by a source circuit having at least two inverted pulse signal supply terminals. The circuit includes a first counter to count pulses of a first pulse signal and supply a first count and a second counter to count pulses of a second pulse signal and supply a second count. A selection circuit selects one of the first and second counts.

In accordance with an embodiment, a method includes receiving a first differential logic signal using a first branch of a circuit that extends from a voltage supply of the circuit as far as an earth terminal of the circuit and has at least one first differential transistor pair, receiving a second differential logic signal using a second branch of the circuit that extends from the voltage supply to the earth terminal and has at least one second differential transistor pair, conducting a current flow between the first branch and the second branch, and outputting an output signal by the second branch.

A circuit includes a clock generator, a frequency divider, and a first biasing circuit. The clock generator generates a clock signal of a first frequency. The frequency divider includes a first pair of cross coupled transistors. The frequency divider produces the clock signal of a second frequency. The first biasing circuit is coupled with the first pair of cross coupled transistors of the frequency divider. The first biasing circuit is adapted to enable a change in a transconductance of the first pair of cross coupled transistors to stabilize a phase angle between the clock signal at the first frequency and the clock signal at the second frequency.

Some embodiments include apparatuses and methods of operating such apparatuses. One of the apparatuses includes a first circuit included in a phase-locked loop (PLL) to receive an input clock signal and a feedback clock signal, and to generate an output clock signal; a second circuit included in the PLL to generate the feedback clock signal from the output clock signal; and a third circuit to prevent the output clock signal from toggling during a portion of a time interval when the PLL performs an operation of aligning phases of the input clock signal and feedback clock signal.

Some embodiments include apparatuses and methods of operating such apparatuses. One of the apparatuses includes a first circuit included in a phase-locked loop (PLL) to receive an input clock signal and a feedback clock signal, and to generate an output clock signal; a second circuit included in the PLL to generate the feedback clock signal from the output clock signal; and a third circuit to prevent the output clock signal from toggling during a portion of a time interval when the PLL performs an operation of aligning phases of the input clock signal and feedback clock signal.