Circuits and systems for generating counter signals are provided herein. A circuit may comprise a shift register having a series of flip-flops. Each of the flip-flops of the series may be coupled to a clock. The shift register may generate a borrowing clock signal using an output of a flip-flop of the shift register, and a transition of the borrowing clock signal may be advanced by a number of clock cycles based on a position of the flip-flop of the shift register. The circuit may further comprise a clock divider circuit having a number of divide-by-N counters and a number of flip-flops. A divide-by-N counter may be coupled to a flip-flop of the shift register, and a flip-flop of the clock divider circuit may be coupled to one of the divide-by-N counters and to the clock.

A synchronous divider circuit with time-synchronized outputs. The synchronous divider circuit includes a plurality of divider stages including each a D-flip-flop circuit and a respective retiming flip-flop circuit, wherein an output terminal of the retiming flip-flop circuit of a current divider stage is connected to an input of the D-flip-flop circuit of a next divider stage, and wherein the current divider stage includes an additional retiming flip-flop circuit, wherein the output terminal of the retiming flip-flop circuit of the current divider stage is connected to an input terminal of the additional retiming flip-flop circuit of the current divider stage, so that an output signal of the additional retiming flip-flop circuit of the current divider stage and an output terminal of the retiming flip-flop circuit of the next divider stage are time-synchronized with respect to each other.

Circuits and systems for generating counter signals are provided herein. A circuit may comprise a shift register having a series of flip-flops. Each of the flip-flops of the series may be coupled to a clock. The shift register may generate a borrowing clock signal using an output of a flip-flop of the shift register, and a transition of the borrowing clock signal may be advanced by a number of clock cycles based on a position of the flip-flop of the shift register. The circuit may further comprise a clock divider circuit having a number of divide-by-N counters and a number of flip-flops. A divide-by-N counter may be coupled to a flip-flop of the shift register, and a flip-flop of the clock divider circuit may be coupled to one of the divide-by-N counters and to the clock.

A code generator includes an asynchronous counter that includes first to m-th flip-flops configured to asynchronously output first to m-th output signals in response to a first clock signal, the first to m-th output signals corresponding to first to m-th bits (m being an integer of 2 or more) of a code, respectively, and a synchronous counter that includes (m+1)-th to (m+n)-th flip-flops configured to synchronously output (m+1)-th to (m+n)-th output signals in response to the first clock signal, the (m+1)-th to (m+n)-th output signals corresponding to (m+1)-th to (m+n)-th bits (n being an integer of 2 or more) of the code. The asynchronous counter further includes first to m-th delay circuits configured to respectively delay the first to m-th output signals such that the first to m-th bits of the code are output together at the same time when the (m+1)-th to (m+n)-th bits are output.

A code generator includes an asynchronous counter that includes first to m-th flip-flops configured to asynchronously output first to m-th output signals in response to a first clock signal, the first to m-th output signals corresponding to first to m-th bits (m being an integer of 2 or more) of a code, respectively, and a synchronous counter that includes (m+1)-th to (m+n)-th flip-flops configured to synchronously output (m+1)-th to (m+n)-th output signals in response to the first clock signal, the (m+1)-th to (m+n)-th output signals corresponding to (m+1)-th to (m+n)-th bits (n being an integer of 2 or more) of the code. The asynchronous counter further includes first to m-th delay circuits configured to respectively delay the first to m-th output signals such that the first to m-th bits of the code are output together at the same time when the (m+1)-th to (m+n)-th bits are output.

An apparatus includes a plurality of latches and a plurality of logic gates. Each latch may be setable and resettable. The logic gates may be connected to the latches to form a multi-modulus divider that generates an output clock signal by dividing an input clock signal in response to a command signal. Each latch may be commanded into a corresponding initial state while the command signal is in an initialization state. Each latch is generally free to change states while the command signal is in a run state. A modulus division operation of the multi-modulus divider may start upon an initial edge of the input clock signal after the command signal changes from the initialization state to the run state.

An apparatus is described. The apparatus includes a counter circuit having ordered state element circuits where a respective clock input of a state element circuit is fed by a data output of a preceding lower ordered bit state element. The counter circuit also being programmable to enable different amounts to be counted by the counter circuit, wherein respective reload values for the amounts are received at the state elements as a respective asynchronous set or reset.

An apparatus includes a plurality of latches and a plurality of logic gates. Each latch may be setable and resettable. The logic gates may be connected to the latches to form a multi-modulus divider that generates an output clock signal by dividing an input clock signal in response to a command signal. Each latch may be commanded into a corresponding initial state while the command signal is in an initialization state. Each latch is generally free to change states while the command signal is in a run state. A modulus division operation of the multi-modulus divider may start upon an initial edge of the input clock signal after the command signal changes from the initialization state to the run state.

An apparatus is described. The apparatus includes a counter circuit having ordered state element circuits where a respective clock input of a state element circuit is fed by a data output of a preceding lower ordered bit state element. The counter circuit also being programmable to enable different amounts to be counted by the counter circuit, wherein respective reload values for the amounts are received at the state elements as a respective asynchronous set or reset.

Described is an apparatus of a quadrature divider. The apparatus is independent of a jam latch, and is for generating a quadrature clock. The apparatus comprises: a first selection unit controllable by a clock signal, the first selection unit to directly or indirectly generate a first phase of the quadrature clock; a third selection unit controllable by the clock signal, the third selection unit to receive the first phase of the quadrature clock, the third selection unit to directly or indirectly generate a third phase of the quadrature clock, wherein the first selection unit to receive the third phase of the quadrature clock.