A frequency divider unit to receive an oscillating signal and to update, at an output of the frequency divider unit, a frequency-divided oscillating signal is presented. The frequency divider unit has a first clocked signal inverter to update, clocked based on the oscillating signal, a first intermediate signal at an output of the first clocked signal inverter. The frequency divider unit has a second clocked signal inverter, wherein the output of the first clocked signal inverter may be connected to an input of the second clocked signal inverter, and wherein the second clocked signal inverter updates, clocked based on the oscillating signal, a second intermediate signal at an output of the second clocked signal inverter. The frequency divider unit has a continuously operating signal inverter coupled between the output of the second clocked signal inverter and the input of the first clocked signal inverter.

Disclosed is an N-bit counter including: an N-bit counting circuit starting counting from an initial value to generate a count value composed of N bits, and being loaded with the initial value to restart counting from the initial value when a reload signal changes from a first reload level to a second reload level; a reload signal generating circuit having the reload signal change from the first reload level to the second reload level when the logical conjunction of K bit(s) among the N bits changes from a first value to a second value; and a reset circuit having a reset signal change from a first reset level to a second reset level so as to have the reload signal change from the second reload level to the first reload level and thereby allow the N-bit counting circuit to restart counting.

Disclosed is an N-bit counter including: an N-bit counting circuit starting counting from an initial value to generate a count value composed of N bits, and being loaded with the initial value to restart counting from the initial value when a reload signal changes from a first reload level to a second reload level; a reload signal generating circuit having the reload signal change from the first reload level to the second reload level when the logical conjunction of K bit(s) among the N bits changes from a first value to a second value; and a reset circuit having a reset signal change from a first reset level to a second reset level so as to have the reload signal change from the second reload level to the first reload level and thereby allow the N-bit counting circuit to restart counting.

A divider and buffer circuit uses a receive command to initiate a reset of buffer circuitry prior to restarting to avoid a metastable state. For example, the divider and buffer circuit includes a first buffer circuit, a second buffer circuit, and a reset circuit. The reset circuit receives a command and provide a pulse on a reset signal in response to the command. In response to the reset pulse, the first buffer circuit provides a first divided clock signal having a first logical value based on respective logical values of received complementary clock signals and the second buffer circuit provides a second divided clock signal having a second logical value based on the respective logical values of the complementary clock signals. The command is a CAS SYNC command, in some examples.

A divider and buffer circuit uses a receive command to initiate a reset of buffer circuitry prior to restarting to avoid a metastable state. For example, the divider and buffer circuit includes a first buffer circuit, a second buffer circuit, and a reset circuit. The reset circuit receives a command and provide a pulse on a reset signal in response to the command. In response to the reset pulse, the first buffer circuit provides a first divided clock signal having a first logical value based on respective logical values of received complementary clock signals and the second buffer circuit provides a second divided clock signal having a second logical value based on the respective logical values of the complementary clock signals. The command is a CAS SYNC command, in some examples.

A method for reducing deterministic jitter in a clock generator includes providing a load current through a regulated voltage node to a circuit responsive to a divide ratio. The method includes providing an auxiliary current through the regulated voltage node. The auxiliary current has a first current level during a first period corresponding to a first value of the divide ratio and the auxiliary current has a second current level during a second period corresponding to a second value of the divide ratio.

A method for reducing deterministic jitter in a clock generator includes providing a load current through a regulated voltage node to a circuit responsive to a divide ratio. The method includes providing an auxiliary current through the regulated voltage node. The auxiliary current has a first current level during a first period corresponding to a first value of the divide ratio and the auxiliary current has a second current level during a second period corresponding to a second value of the divide ratio.

A multi-modulus frequency divider circuit includes first and second frequency division stages. The first frequency division stage receives a first input clock signal having a first oscillating frequency, a first modulus input signal, and a first division bit. The first frequency division stage divides the first oscillating frequency by a first division ratio, and generates a second input clock signal having a second oscillating frequency. The second frequency division stage receives the second input clock signal, a second modulus input signal, and a second division bit. The second frequency division stage generates an output clock signal having an output oscillating frequency by dividing the second oscillating frequency by a second division ratio.

A multi-modulus frequency divider circuit includes first and second frequency division stages. The first frequency division stage receives a first input clock signal having a first oscillating frequency, a first modulus input signal, and a first division bit. The first frequency division stage divides the first oscillating frequency by a first division ratio, and generates a second input clock signal having a second oscillating frequency. The second frequency division stage receives the second input clock signal, a second modulus input signal, and a second division bit. The second frequency division stage generates an output clock signal having an output oscillating frequency by dividing the second oscillating frequency by a second division ratio.

A programmable clock divider having reset circuits configured to receive a DP count comprises a first flip-flop having a clock input, a first output, and one of the DP inputs configured to receive a clock signal, a plurality of flip-flops connected to form a ripple counter configured to each receive a DP input, a clock input, and a reset input to provide a first output coupled to the clock input of a subsequent flip-flop of the plurality of flip-flops, each subsequent flip-flop having its clock input coupled to the first output of the preceding flip-flop, a first reset circuit coupled to the flip-flops configured to provide an out signal in response to the flip-flops obtaining the DP count, and a second reset circuit configured to provide a reset signal to the reset input of the plurality of flip-flops in response to the out signal from the first reset circuit.