A programmable clock divider having reset circuits configured to receive a DP count comprises a first flip-flop having a clock input, a first output, and one of the DP inputs configured to receive a clock signal, a plurality of flip-flops connected to form a ripple counter configured to each receive a DP input, a clock input, and a reset input to provide a first output coupled to the clock input of a subsequent flip-flop of the plurality of flip-flops, each subsequent flip-flop having its clock input coupled to the first output of the preceding flip-flop, a first reset circuit coupled to the flip-flops configured to provide an out signal in response to the flip-flops obtaining the DP count, and a second reset circuit configured to provide a reset signal to the reset input of the plurality of flip-flops in response to the out signal from the first reset circuit.

According to one embodiment, there is provided a clock generator including a frequency divider configured to generate a divided frequency clock of a frequency lower than that of a source clock by performing mask processing on part of a pulse train of the source clock.

A method for reducing deterministic jitter in a clock generator includes providing a load current through a regulated voltage node to a circuit responsive to a divide ratio. The method includes providing an auxiliary current through the regulated voltage node. The auxiliary current has a first current level during a first period corresponding to a first value of the divide ratio and the auxiliary current has a second current level during a second period corresponding to a second value of the divide ratio.

A method for reducing deterministic jitter in a clock generator includes providing a load current through a regulated voltage node to a circuit responsive to a divide ratio. The method includes providing an auxiliary current through the regulated voltage node. The auxiliary current has a first current level during a first period corresponding to a first value of the divide ratio and the auxiliary current has a second current level during a second period corresponding to a second value of the divide ratio.

Disclosed is an N-bit counter including: an N-bit counting circuit starting counting from an initial value to generate a count value composed of N bits, and being loaded with the initial value to restart counting from the initial value when a reload signal changes from a first reload level to a second reload level; a reload signal generating circuit having the reload signal change from the first reload level to the second reload level when the logical conjunction of K bit(s) among the N bits changes from a first value to a second value; and a reset circuit having a reset signal change from a first reset level to a second reset level so as to have the reload signal change from the second reload level to the first reload level and thereby allow the N-bit counting circuit to restart counting.

Disclosed is an N-bit counter including: an N-bit counting circuit starting counting from an initial value to generate a count value composed of N bits, and being loaded with the initial value to restart counting from the initial value when a reload signal changes from a first reload level to a second reload level; a reload signal generating circuit having the reload signal change from the first reload level to the second reload level when the logical conjunction of K bit(s) among the N bits changes from a first value to a second value; and a reset circuit having a reset signal change from a first reset level to a second reset level so as to have the reload signal change from the second reload level to the first reload level and thereby allow the N-bit counting circuit to restart counting.

A clock circuit includes a circuit configured to use a regulated voltage on a regulated voltage node to provide a frequency modulated clock signal having a frequency vacillating between a first frequency and a second frequency. The clock circuit includes an auxiliary loading circuit coupled to the regulated voltage node and configured to selectively provide load compensation for a load difference of the circuit. The load difference is a difference between a first load corresponding to the first frequency and a second load corresponding to the second frequency. The circuit may include a frequency divider circuit configured to use the regulated voltage on the regulated voltage node to generate the frequency modulated clock signal by frequency dividing an input clock signal according to a divide value vacillating between a first divide value and a second divide value.

A clock circuit includes a circuit configured to use a regulated voltage on a regulated voltage node to provide a frequency modulated clock signal having a frequency vacillating between a first frequency and a second frequency. The clock circuit includes an auxiliary loading circuit coupled to the regulated voltage node and configured to selectively provide load compensation for a load difference of the circuit. The load difference is a difference between a first load corresponding to the first frequency and a second load corresponding to the second frequency. The circuit may include a frequency divider circuit configured to use the regulated voltage on the regulated voltage node to generate the frequency modulated clock signal by frequency dividing an input clock signal according to a divide value vacillating between a first divide value and a second divide value.

An apparatus includes a control circuit configured to generate a frequency divider control signal approximating a fractional divide ratio. The apparatus includes a frequency divider configured to generate an output clock signal based on an input clock signal and an adjusted frequency divider control signal. The output clock signal is a frequency-divided version of the input clock signal. The apparatus includes a measurement circuit configured to provide digital time information corresponding to an edge of the output clock signal. The apparatus includes an adaptive adjustment circuit configured to generate the adjusted frequency divider control signal based on the frequency divider control signal and the digital time information.

A setting data output circuit (3) is configured to update setting data in synchronization with a frequency divided signal output from a dual modulus frequency divider on a last stage out of the dual modulus frequency dividers to which a non-significant reset signal is output from a reset circuit (6) which are included in a plurality of dual modulus frequency dividers (1-1 and 1-2) in a first frequency divider group (1). As a result, when a frequency dividing ratio of the dual modulus frequency divider on the last stage out of valid dual modulus frequency dividers contributing to frequency dividing operation is 3, it is possible to realize normal frequency dividing operation even in a case in which frequency dividing ratio setting data to decrease the number of valid dual modulus frequency dividers contributing to the frequency dividing operation is provided.