A multi-modulus frequency divider circuit includes first and second frequency division stages. The first frequency division stage receives a first input clock signal having a first oscillating frequency, a first modulus input signal, and a first division bit. The first frequency division stage divides the first oscillating frequency by a first division ratio, and generates a second input clock signal having a second oscillating frequency. The second frequency division stage receives the second input clock signal, a second modulus input signal, and a second division bit. The second frequency division stage generates an output clock signal having an output oscillating frequency by dividing the second oscillating frequency by a second division ratio.

An illustrative PLL circuit and method for generating a clock signal over a wide frequency range without gaps. In one illustrative embodiment, an extended-range PLL includes: a phase comparator that determines a phase error between a reference clock and a feedback clock; a loop filter that converts the phase error into a control signal; a voltage controlled oscillator (VCO) that provides a generated clock signal having a generated clock frequency determined by the control signal; a divide-by-1.5 block that produces a reduced-frequency clock signal in response to the generated clock signal; and a multiplexer that selects one of the generated clock signal and the reduced-frequency clock signal as a selected clock signal.

A clock generating device includes a divisor register, a reference clock generator, a first counter, a second counter, and a delay regulator circuit. The divisor register provides a divisor. The reference clock generator outputs a reference clock signal. The first counter counts a first number of cycles of the reference clock signal and generates a first count. The first counter outputs a first clock signal according to the first count and the divisor. The second counter counts a second number of cycles of the first clock signal and generates a second count. The second counter outputs a second clock signal according to the second count and a coefficient. The delay regulator circuit determines whether to control the first counter to delay outputting the first clock signal according to the first clock signal.

A clock generating device includes a divisor register, a reference clock generator, a first counter, a second counter, and a delay regulator circuit. The divisor register provides a divisor. The reference clock generator outputs a reference clock signal. The first counter counts a first number of cycles of the reference clock signal and generates a first count. The first counter outputs a first clock signal according to the first count and the divisor. The second counter counts a second number of cycles of the first clock signal and generates a second count. The second counter outputs a second clock signal according to the second count and a coefficient. The delay regulator circuit determines whether to control the first counter to delay outputting the first clock signal according to the first clock signal.

The invention relates to a frequency multiplying device for determination of a fundamental frequency f of an analogue target signal. The device comprises a generating device for generating a reference signal having a frequency f.sub.OSC, wherein f.sub.OSC is greater than f, and a first counter being coupled to a terminal, the terminal to be fed with the analogue target signal, and being coupled to the generating device such that the first counter counts a number of signal edges generated from the reference signal in a time interval corresponding substantially to 1/f and outputs a first counter signal, wherein a frequency divider is coupled between the generating device and the first counter and a second counter is coupled to the generating device for counting signal edges of a signal generated from the reference signal the second counter outputting a second counter signal and a comparator is coupled to the first counter to receive the first counter signal and coupled to the second counter to receive the second counter signal, wherein the comparator generates a signal in the event the first counter signal is equal to the second counter signal, and the output of the comparator is coupled to reset the second counter.

A full quadrant analog interpolator used in a fractional clock generator. A quadrature clock signal with minimal jitter is provided to the full quadrant analog interpolator. The full quadrant analog interpolator uses a series of switches and current sources to develop a differential output signal based on a digital input value, thus allowing digital control of the delay developed by the full quadrant analog interpolator. The differential output of the full quadrant analog interpolator is provided to multi-stage comparator. The output of the multi-stage comparator is provided to an integer divider to provide the final output clock. A digital control section utilizes a modulator and a summer to utilize an input N. control input which provides the desired fractional division amount to provide a signal to a phase accumulator. The output of the phase accumulator is the digital control or value of the full quadrant analog interpolator.

A full quadrant analog interpolator used in a fractional clock generator. A quadrature clock signal with minimal jitter is provided to the full quadrant analog interpolator. The full quadrant analog interpolator uses a series of switches and current sources to develop a differential output signal based on a digital input value, thus allowing digital control of the delay developed by the full quadrant analog interpolator. The differential output of the full quadrant analog interpolator is provided to multi-stage comparator. The output of the multi-stage comparator is provided to an integer divider to provide the final output clock. A digital control section utilizes a modulator and a summer to utilize an input N. control input which provides the desired fractional division amount to provide a signal to a phase accumulator. The output of the phase accumulator is the digital control or value of the full quadrant analog interpolator.

Exemplary embodiments include an electronic frequency-divider circuit comprising a multi-phase generator circuit configured to: receive an oscillating input signal having a frequency f; determine an integer divide ratio Q based on a first control signal input; and based on the oscillating input signal, generate an N-phase output signal having a frequency f-divided-by-M, wherein M is an integer and adjacent phases of the N-phase output signal are separated by 360-divided-by-(M-times-Q) degrees. The divider circuit can also include a control circuit configured to receive a control input and, based on the control input: provide the first control signal to the multi-phase generator circuit; and select a particular phase of the N-phase output signal. Exemplary embodiments also include a phase-locked loop circuits, transceiver circuits, radio stations, and methods of frequency-dividing an oscillating signal.

A full quadrant analog interpolator used in a fractional clock generator. A quadrature clock signal with minimal jitter is provided to the full quadrant analog interpolator. The full quadrant analog interpolator uses a series of switches and current sources to develop a differential output signal based on a digital input value, thus allowing digital control of the delay developed by the full quadrant analog interpolator. The differential output of the full quadrant analog interpolator is provided to multi-stage comparator. The output of the multi-stage comparator is provided to an integer divider to provide the final output clock. A digital control section utilizes a modulator and a summer to utilize an input N. control input which provides the desired fractional division amount to provide a signal to a phase accumulator. The output of the phase accumulator is the digital control or value of the full quadrant analog interpolator.

A full quadrant analog interpolator used in a fractional clock generator. A quadrature clock signal with minimal jitter is provided to the full quadrant analog interpolator. The full quadrant analog interpolator uses a series of switches and current sources to develop a differential output signal based on a digital input value, thus allowing digital control of the delay developed by the full quadrant analog interpolator. The differential output of the full quadrant analog interpolator is provided to multi-stage comparator. The output of the multi-stage comparator is provided to an integer divider to provide the final output clock. A digital control section utilizes a modulator and a summer to utilize an input N. control input which provides the desired fractional division amount to provide a signal to a phase accumulator. The output of the phase accumulator is the digital control or value of the full quadrant analog interpolator.