A fractional-N frequency synthesizer comprising a multi-phase generator, a multi-path error phase generator; a current combiner; a loop filter connected to the current combiner; an oscillator (150) connected to the loop filter; a frequency divider (160); a SDM connected to both the frequency divider and the multi-phase generator, to generate variable division ratio.

A fractional-N frequency synthesizer comprising a multi-phase generator, a multi-path error phase generator; a current combiner; a loop filter connected to the current combiner; an oscillator (150) connected to the loop filter; a frequency divider (160); a SDM connected to both the frequency divider and the multi-phase generator, to generate variable division ratio.

In accordance with an embodiment, a circuit includes an input clock terminal, an output clock terminal, a first input data terminal, and a set of input data terminals having a number of terminals. A divide-by-two block is coupled to the output clock terminal. A modular one-shot clock divider is coupled between the input clock terminal and the divide-by-two block. The modular one-shot clock divider is further coupled to the set of input data terminals. An intermediate clock generation block is coupled between the input clock terminal and the modular one-shot clock divider. The intermediate clock generation block includes a first digital logic block coupled between the input clock terminal and the modular one-shot clock divider. The first digital logic block is further coupled to the first input data terminal, and a clock-blocking block is coupled between the divide-by-two block and the first digital logic block.

Exemplary embodiments include an electronic frequency-divider circuit comprising a multi-phase generator circuit configured to: receive an oscillating input signal having a frequency f; determine an integer divide ratio Q based on a first control signal input; and based on the oscillating input signal, generate an N-phase output signal having a frequency f-divided-by-M, wherein M is an integer and adjacent phases of the N-phase output signal are separated by 360-divided-by-(M-times-Q) degrees. The divider circuit can also include a control circuit configured to receive a control input and, based on the control input: provide the first control signal to the multi-phase generator circuit; and select a particular phase of the N-phase output signal. Exemplary embodiments also include a phase-locked loop circuits, transceiver circuits, radio stations, and methods of frequency-dividing an oscillating signal.

A clock divider includes, in part, a pair of counters and a programmable delay line. A first one of the counters operates at a first frequency and is configured to count using a first integer portion of the divisor. The second counter operates at a second frequency smaller than the first frequency and is configured to count using a second integer portion of the divisor. The programmable delay includes, in part, a chain of delay elements configured to generate a multitude of delays at the output of the second counter. A multiplexer selects one of the generated delays in accordance with the fractional portion of the divisor. The second counter increases its count only when the first counter reaches a terminal count. The first and second integer portions are loaded respectively into the first and second counters when the second counter reaches its terminal count.

A clock divider includes, in part, a pair of counters and a programmable delay line. A first one of the counters operates at a first frequency and is configured to count using a first integer portion of the divisor. The second counter operates at a second frequency smaller than the first frequency and is configured to count using a second integer portion of the divisor. The programmable delay includes, in part, a chain of delay elements configured to generate a multitude of delays at the output of the second counter. A multiplexer selects one of the generated delays in accordance with the fractional portion of the divisor. The second counter increases its count only when the first counter reaches a terminal count. The first and second integer portions are loaded respectively into the first and second counters when the second counter reaches its terminal count.

An electronic circuit arranged to receive an oscillating signal and output an output signal at a frequency having a frequency relation with the oscillating signal defined by a divide ratio is provided. The electronic circuit comprises a first frequency divider arranged to receive the oscillating signal and output N frequency divided signals of different phases, a second frequency divider arranged to receive one of the N signals and frequency divide the received signal by a value given by a first control signal provided to the second frequency divider, N latch circuits each being arranged to receive a respective one of the N signals at a clocking input of the respective latch circuit and to receive an output of the second frequency divider at an input of the respective latch circuit, a multiplexer circuit arranged to receive outputs of the N latch circuits and to output a signal, on which the output signal is based, selected from the received signals based on a second control signal provided to the multiplexer circuit, and a control circuit arranged to provide the first control signal and the second control signal based on the divide ratio. A phase-locked loop circuit, a transceiver circuit, a radio station, and a method of frequency dividing an oscillating signal are also provided.

A fractional-N frequency synthesizer comprising a multi-phase generator, a multi-path error phase generator; a current combiner; a loop filter connected to the current combiner; an oscillator (150) connected to the loop filter; a frequency divider (160); a SDM connected to both the frequency divider and the multi-phase generator, to generate variable division ratio.

A clock divider includes, in part, a pair of counters and a programmable delay line. A first one of the counters operates at a first frequency and is configured to count using a first integer portion of the divisor. The second counter operates at a second frequency smaller than the first frequency and is configured to count using a second integer portion of the divisor. The programmable delay line includes, in part, a chain of delay elements configured to generate a multitude of delays of the output of the second counter. A multiplexer selects one of the generated delays in accordance with the fractional portion of the divisor. The second counter increases its count only when the first counter reaches a terminal count. The first and second integer portions are loaded respectively into the first and second counters when the second counter reaches its terminal count.

A clock divider includes, in part, a pair of counters and a programmable delay line. A first one of the counters operates at a first frequency and is configured to count using a first integer portion of the divisor. The second counter operates at a second frequency smaller than the first frequency and is configured to count using a second integer portion of the divisor. The programmable delay line includes, in part, a chain of delay elements configured to generate a multitude of delays of the output of the second counter. A multiplexer selects one of the generated delays in accordance with the fractional portion of the divisor. The second counter increases its count only when the first counter reaches a terminal count. The first and second integer portions are loaded respectively into the first and second counters when the second counter reaches its terminal count.