Fast turn-on protection of a cascode switch is presented herein. A cascode circuit includes a depletion mode field effect transistor and an enhancement mode field effect transistor electrically coupled in cascode. During turn-on, a protection circuit detects an overcurrent fault by observing a plateau of a cascode node voltage. An overcurrent fault may be detected in response to the plateau existing for greater than a threshold time duration.

Fast turn-on protection of a cascode switch is presented herein. A cascode circuit includes a depletion mode field effect transistor and an enhancement mode field effect transistor electrically coupled in cascode. During turn-on, a protection circuit detects an overcurrent fault by observing a plateau of a cascode node voltage. An overcurrent fault may be detected in response to the plateau existing for greater than a threshold time duration.

An integrated circuit for a switching power supply circuit has an enable pin, a power supply pin, a switch pin, a ground pin, a power switch and an amplifier. The enable pin receives an enable signal. The power supply pin is coupled to a power supply capacitor. The switch pin receives an input voltage. The power switch has a normally-on switching device and a normally-off switching device. A first terminal of the normally-on switching device is coupled to the switch pin. A first terminal of the normally-off switching device is coupled to a second terminal of the normally-on switching device, a second terminal of the normally-off switching device is coupled to the ground pin. The amplifier provides an amplified signal based on a difference between a voltage at the power supply pin and a voltage at the second terminal of the normally-on switching device to control the normally-on switching device.

A cascode semiconductor device comprise a normally-on high-voltage (HV) silicon carbide (SiC) junction field-effect transistor (JFET), a normally-off low-voltage (LV) gallium nitride (GaN) high-electron-mobility transistor (HEMT) and a clamping circuit. The SiC JFET has a first gate terminal, a first drain terminal and a first source terminal. The GaN HEMT has a second gate terminal, a second drain terminal and a second source terminal. The second drain terminal is connected to the first source terminal. The second source terminal is connected to the first gate terminal. The clamping circuit is connected between the second drain terminal and the second gate terminal and has a clamping voltage. The clamping voltage is greater than a magnitude of a threshold voltage of the SiC JFET and smaller than a reverse gate voltage limit of the SiC JFET.

A cascode switch device includes a normally-on switch device, a normally-off switch device, and a gate driver. The normally-on switch device has a first terminal, a second terminal and a control terminal. The normally-off switch device has a first terminal, a second terminal and a control terminal. The first terminal of the normally-off switch device is coupled to the second terminal of the normally-on switch device, and the control terminal of the normally-off switch device is coupled to the control terminal of the normally-on switch device. The gate driver is configured to provide a gate driver signal to the control terminal of the normally-on switch device to control a switching slew rate of a voltage at the first terminal of the normally-on switch device. The normally-on switch device is turned on or turned off in response to the gate driver signal.

Fast turn-on protection of a cascode switch is presented herein. A cascode circuit includes a depletion mode field effect transistor and an enhancement mode field effect transistor electrically coupled in cascode. During turn-on, a protection circuit detects an overcurrent fault by observing a plateau of a cascode node voltage. An overcurrent fault may be detected in response to the plateau existing for greater than a threshold time duration.

A gate driver circuit provides a soft-start current to a gate of a power switch during a soft-start period to soft-start the power switch. The gate driver circuit includes: a first current mirror circuit, configured to mirror a reference current according to a mirror ratio to generate a mirror output current; and a path switch coupled on a signal path between the mirror output current and the soft-start current. The soft-start current is generated according to the mirror output current. The path switch is configured to turn off the signal path when the power switch is off. The mirror ratio of the first current mirror circuit is reduced during a predetermined period in the soft-start period to compensate for a spike caused by the path switch being turned on during the soft-start period, such that the soft-start current is prevented from surging during the soft-start period.

Fast turn-on protection of a cascode switch is presented herein. A cascode circuit includes a depletion mode field effect transistor and an enhancement mode field effect transistor electrically coupled in cascode. During turn-on, a protection circuit detects an overcurrent fault by observing a plateau of a cascode node voltage. An overcurrent fault may be detected in response to the plateau existing for greater than a threshold time duration.

A cascode switch device includes a normally-on switch device, a normally-off switch device, and a gate driver. The normally-on switch device has a first terminal, a second terminal and a control terminal. The normally-off switch device has a first terminal, a second terminal and a control terminal. The first terminal of the normally-off switch device is coupled to the second terminal of the normally-on switch device, and the control terminal of the normally-off switch device is coupled to the control terminal of the normally-on switch device. The gate driver is configured to provide a gate driver signal to the control terminal of the normally-on switch device to control a switching slew rate of a voltage at the first terminal of the normally-on switch device. The normally-on switch device is turned on or turned off in response to the gate driver signal.