In described examples, a feedback loop has phase detection (PD) circuitry that has a reference input to receive a reference frequency signal, a feedback input to receive a feedback signal, and phase difference outputs. A phase to digital converter (P2DC) includes a first phase to charge converter (PCC) that has a gain polarity and a first phase error output; a second PCC that has an opposite gain polarity and a second phase error output. A differential loop filter has an amplifier with an inverting input coupled to the first phase error output and a non-inverting input coupled to the second phase error output. An analog to digital converter (ADC) has an input coupled to an output of the differential loop filter. A feedback path is coupled to the output of the P2DC, with an output of the feedback path providing the feedback signal to the PD feedback input.

In described examples, a feedback loop has phase detection (PD) circuitry that has a reference input to receive a reference frequency signal, a feedback input to receive a feedback signal, and phase difference outputs. A phase to digital converter (P2DC) includes a first phase to charge converter (PCC) that has a gain polarity and a first phase error output; a second PCC that has an opposite gain polarity and a second phase error output. A differential loop filter has an amplifier with an inverting input coupled to the first phase error output and a non-inverting input coupled to the second phase error output. An analog to digital converter (ADC) has an input coupled to an output of the differential loop filter. A feedback path is coupled to the output of the P2DC, with an output of the feedback path providing the feedback signal to the PD feedback input.

An oscillator includes a resonator and a first loop circuit. The first loop circuit includes an amplifier and a first coupler. That first loop circuit is electrically coupled to the resonator. The oscillator is configured to produce negative feedback for the amplifier in a cavity mode relative to short circuit terminations or open circuit terminations of a cavity modelling the oscillator at frequencies offset from a carrier frequency. The oscillator has a loss of less than 4.00 dB for a bidirectional trip through the cavity at the frequencies offset from the carrier frequency.

An oscillator includes a resonator and a first loop circuit. The first loop circuit includes an amplifier and a first coupler. That first loop circuit is electrically coupled to the resonator. The oscillator is configured to produce negative feedback for the amplifier in a cavity mode relative to short circuit terminations or open circuit terminations of a cavity modelling the oscillator at frequencies offset from a carrier frequency. The oscillator has a loss of less than 4.00 dB for a bidirectional trip through the cavity at the frequencies offset from the carrier frequency.

An oscillator is configured to generate a signal with a frequency sweep, the oscillator having circuitry comprising a set of capacitors, each capacitor of the set of capacitors being switchably connectable in parallel in the circuitry so that the frequency of the signal has an intrinsic dependence on the number of the capacitors connected, a shift register controllable by a clock line and comprising a number of bits, each bit of the number of bits controlling connection of a respective capacitor of the set of capacitors so that the capacitors are connectable or disconnectable in a pre-determined order by shifting, respectively, activation or de-activation bits into the shift register, wherein the shifting is paced by the clock line; and a clock signal generator configured to output a clock signal with a time modulation on the clock line.

An oscillator is configured to generate a signal with a frequency sweep, the oscillator having circuitry comprising a set of capacitors, each capacitor of the set of capacitors being switchably connectable in parallel in the circuitry so that the frequency of the signal has an intrinsic dependence on the number of the capacitors connected, a shift register controllable by a clock line and comprising a number of bits, each bit of the number of bits controlling connection of a respective capacitor of the set of capacitors so that the capacitors are connectable or disconnectable in a pre-determined order by shifting, respectively, activation or de-activation bits into the shift register, wherein the shifting is paced by the clock line; and a clock signal generator configured to output a clock signal with a time modulation on the clock line.

A novel voltage controlled oscillator (VCO) based on complementary current-injection field-effect transistor (CiFET) devices is disclosed. The VCO includes an odd number stages of rings, each of rings comprises a CiFET.

A novel voltage controlled oscillator (VCO) based on complementary current-injection field-effect transistor (CiFET) devices is disclosed. The VCO includes an odd number stages of rings, each of rings comprises a CiFET.

In described examples, a phase measurement circuit includes a first switch coupled between a power terminal and a phase measurement output, the first switch having a first switch control terminal coupled to an up input. The phase measurement circuit includes a second switch coupled between the phase measurement output, the second switch having a second switch control terminal coupled to a down input. The phase measurement circuit includes a first capacitor coupled between the power terminal and the phase measurement output, a second capacitor coupled between the phase measurement output and a ground terminal, and a charge pump circuit having a first control input, a second control input, and a charge pump output, the first control input coupled to the up input, the second control input coupled to the down input, and the charge pump output coupled to the phase measurement output.

In described examples, a phase measurement circuit includes a first switch coupled between a power terminal and a phase measurement output, the first switch having a first switch control terminal coupled to an up input. The phase measurement circuit includes a second switch coupled between the phase measurement output, the second switch having a second switch control terminal coupled to a down input. The phase measurement circuit includes a first capacitor coupled between the power terminal and the phase measurement output, a second capacitor coupled between the phase measurement output and a ground terminal, and a charge pump circuit having a first control input, a second control input, and a charge pump output, the first control input coupled to the up input, the second control input coupled to the down input, and the charge pump output coupled to the phase measurement output.