The present invention relates to passive phased injection locked circuit and ring-based voltage controlled oscillators. A passive phased injection locked circuit comprises first and second transmission lines, each has a plurality of discrete elements, that are operative to delay the phase of AC signal. Between the first and second transmission lines, a capacitor network is formed to advance the phases of the AC signal in concert along the transmission lines. For the ring-based voltage controlled oscillators, each of the first and second transmission lines has an odd number of discrete elements.

The present invention relates to passive phased injection locked circuit and ring-based voltage controlled oscillators. A passive phased injection locked circuit comprises first and second transmission lines, each has a plurality of discrete elements, that are operative to delay the phase of AC signal. Between the first and second transmission lines, a capacitor network is formed to advance the phases of the AC signal in concert along the transmission lines. For the ring-based voltage controlled oscillators, each of the first and second transmission lines has an odd number of discrete elements.

The present disclosure relates to a phase-locked loop (PLL) based on a charge-sharing locking technique, capable of both fractional-N and integer-N operation. The PLL comprises a voltage pre-setting stage; an oscillator: a shared capacitive load; and a switching network configured for selectively connecting the voltage pre-setting stage to the shared capacitive load during a voltage pre-setting stage for applying an expectant voltage to the capacitive load. The switching network is being further configured for selectively connecting the capacitive load to the oscillator during a charge-sharing locking stage for correcting a phase error in response to a difference between the expected voltage of the capacitor and the voltage of the oscillator. Frequency-tracking and waveform-learning stages are also provided for maintaining PVT (process, voltage, temperature) robustness and for suppressing fractional-N spur, respectively.

The present disclosure relates to a phase-locked loop (PLL) based on a charge-sharing locking technique, capable of both fractional-N and integer-N operation. The PLL comprises a voltage pre-setting stage; an oscillator: a shared capacitive load; and a switching network configured for selectively connecting the voltage pre-setting stage to the shared capacitive load during a voltage pre-setting stage for applying an expectant voltage to the capacitive load. The switching network is being further configured for selectively connecting the capacitive load to the oscillator during a charge-sharing locking stage for correcting a phase error in response to a difference between the expected voltage of the capacitor and the voltage of the oscillator. Frequency-tracking and waveform-learning stages are also provided for maintaining PVT (process, voltage, temperature) robustness and for suppressing fractional-N spur, respectively.

An apparatus includes a phase interpolator configured to receive a four-phase signal and output a six-phase signal, and a summing network configured to receive the six-phase signal and output a two-phase signal, wherein: a first phase, a third phase, and a fifth phase of the six-phase signal are summed to generate a second phase of the two-phase signal, while a second phase, a fourth phase, and a sixth phase of the six-phase signal are summed to generate a first phase of the two-phase signal.

An apparatus includes a phase interpolator configured to receive a four-phase signal and output a six-phase signal, and a summing network configured to receive the six-phase signal and output a two-phase signal, wherein: a first phase, a third phase, and a fifth phase of the six-phase signal are summed to generate a second phase of the two-phase signal, while a second phase, a fourth phase, and a sixth phase of the six-phase signal are summed to generate a first phase of the two-phase signal.

A method includes identifying a design area for a microelectronic device, where the design area includes a plurality of sub-units, each sub-unit from the plurality of sub-units capable of receiving a control signal. The method places a central latch in a center of the design area, where the central latch presents a connection point on a first level of the design area. Responsive to determining a sub-unit of the plurality of sub-units does not include a latch, the method creates a horizontal and vertical axis through the central latch, where the horizontal and vertical axis are bound by a perimeter of the design area. The method places a first set of latches for tiles created by the horizontal axis and the vertical axis on a second level of the design area, where each latch of the first set of latches is placed in a center of a single tile.

A method includes identifying a design area for a microelectronic device, where the design area includes a plurality of sub-units, each sub-unit from the plurality of sub-units capable of receiving a control signal. The method places a central latch in a center of the design area, where the central latch presents a connection point on a first level of the design area. Responsive to determining a sub-unit of the plurality of sub-units does not include a latch, the method creates a horizontal and vertical axis through the central latch, where the horizontal and vertical axis are bound by a perimeter of the design area. The method places a first set of latches for tiles created by the horizontal axis and the vertical axis on a second level of the design area, where each latch of the first set of latches is placed in a center of a single tile.

An acoustic-wave device with active calibration mechanism is provided. The acoustic-wave device with active calibration mechanism includes at least one adjustable acoustic-wave duplexer, a frequency discriminator and a control circuit. The adjustable acoustic-wave duplexer has a first terminal point, a second terminal point and a third terminal point. The adjustable acoustic-wave duplexer includes a TX filter, an RX filter, a first loop switch and a second loop switch. The first loop switch is used for conducting a first loop. The second loop switch is used for conducting a second loop. The control circuit adjusts the operating frequency of the TX filter according to a first loop calibration signal. The control circuit adjusts the operating frequency of the operating frequency of the RX filter according to the second loop calibration signal.

The present invention relates to passive phased injection locked circuit and ring-based voltage controlled oscillators. passive phased injection locked circuit comprises first and second transmission lines, each has a plurality of discrete elements, that are operative to deley the phase of AC signal. Between the first and second transmission lines, a capacitor network is formed to advance the phases of the AC signal in concert along the transmission lines. For the ring-based voltage controlled oscillators, each of the first and second transmission lines has an odd number of discrete elements.