A circuit and a method for eliminating a spurious signal are provided. The circuit includes a phase detector, a spurious estimation and regeneration device, and a phase shifter. After an actual clock signal containing a spurious signal is obtained, the contained spurious signal is estimated based on the reference clock signal that does not contain the spurious signal. Reverse adjustment is performed on the actual clock signal based on the estimated spurious signal to eliminate the spurious signal in the actual clock signal, ensuring eliminating the generated spurious signal by performing reverse adjustment, improving the signal transmission quality, thereby solving the problem of reduced signal quality due to that the spurious signal cannot be suppressed in generation according to the conventional technology.

A circuit and a method for eliminating a spurious signal are provided. The circuit includes a phase detector, a spurious estimation and regeneration device, and a phase shifter. After an actual clock signal containing a spurious signal is obtained, the contained spurious signal is estimated based on the reference clock signal that does not contain the spurious signal. Reverse adjustment is performed on the actual clock signal based on the estimated spurious signal to eliminate the spurious signal in the actual clock signal, ensuring eliminating the generated spurious signal by performing reverse adjustment, improving the signal transmission quality, thereby solving the problem of reduced signal quality due to that the spurious signal cannot be suppressed in generation according to the conventional technology.

A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low.

A system and method for correcting for phase errors, in a phase locked loop, resulting from spread spectrum clocking involving a reference clock signal having a frequency modulation. A correction generation circuit generates an offset signal, that when injected after the charge pump of the phase locked loop, causes the voltage controlled oscillator to produce a signal with substantially the same frequency modulation, thereby reducing the phase error. The correction generation circuit may include a timing estimation circuit for estimating the times at which transitions (between positive-sloping and negative-sloping portions of the triangle wave) occur, and an amplitude estimation circuit for estimating the amplitude of the offset signal that results in a reduction in the phase error.

A clock generator receives first and second clock signals, and input representing a desired frequency ratio. A comparison is made between frequencies of an output clock signal and the first clock signal, and a first error signal represents the difference between the desired frequency ratio and this comparison result. The first error signal is filtered. A comparison is made between frequencies of the output clock signal and the second clock signal, and a second error signal represents the difference between the filtered first error signal and this comparison result. The second error signal is filtered. A numerically controlled oscillator receives the filtered second error signal and generates an output clock signal. As a result, the output clock signal has the jitter characteristics of the first input clock signal over a useful range of jitter frequencies and the frequency accuracy of the second input clock signal.

A clock generator receives first and second clock signals, and input representing a desired frequency ratio. A comparison is made between frequencies of an output clock signal and the first clock signal, and a first error signal represents the difference between the desired frequency ratio and this comparison result. The first error signal is filtered. A comparison is made between frequencies of the output clock signal and the second clock signal, and a second error signal represents the difference between the filtered first error signal and this comparison result. The second error signal is filtered. A numerically controlled oscillator receives the filtered second error signal and generates an output clock signal. As a result, the output clock signal has the jitter characteristics of the first input clock signal over a useful range of jitter frequencies and the frequency accuracy of the second input clock signal.

Systems and methods are disclosed herein that relate to a wireless device that intelligently uses different reference crystal oscillators (XOs) for a Phase Locked Loop(s) (PLL(s)) in a transceiver of the wireless device. Embodiments of a method of operation of a wireless device comprising a first XO that operates at a first reference frequency and a second XO that operates at a second reference frequency that is greater than the first reference frequency are disclosed. In some embodiments, the method of operation of the wireless devices comprises deciding whether to configure a receiver of the wireless device to use the first XO or the second XO and configuring the receiver of the wireless device to use the first XO or the second XO in accordance with the decision.

An apparatus and method for synchronizing a triggered system to a triggering system by tracking the timing of rising and falling edges of a clock signal at the triggered system and using the tracked timing values for phase shift adjustment of a time base at the triggered systems.

An apparatus and method for synchronizing a triggered system to a triggering system by tracking the timing of rising and falling edges of a clock signal at the triggered system and using the tracked timing values for phase shift adjustment of a time base at the triggered systems.

The disclosure relates to a communication technique for convergence of internet of things (IoT) technology and a 5th generation (5G) or a pre-5G communication system for supporting a higher data transmission rate beyond a 4th generation (4G) communication system, such as the long term evolution (LTE) and a system therefor. The disclosure is applied to intelligent services (for example, smart homes, smart buildings, smart cities, smart cars or connected cars, healthcare, digital education, retail businesses, security-and safety-related services, and the like) based on 5G communication technology and IoT-related technology. A network sharing method and an apparatus for supporting multiple operators in a wireless communication system are provided.