Techniques are disclosed for transferring at least one speech signal of a patient during a magnetic resonance imaging examination, wherein the speech signal is recorded by a speech recording device of a wireless communication device assigned to the patient and transmitted at least as part of a communication signal to a receive device of the magnetic resonance imaging device. The communication signal is a modulated signal or is generated from a modulated signal, and to generate the modulated signal the speech signal is modulated onto a carrier signal. The modulated signal is generated by way of a modulation with reduction of the level of the carrier signal.

A clock generating circuit includes a first frequency multiplier configured to generate a second clock signal having a second frequency based on a first clock signal having a first frequency, and a second frequency multiplier configured to generate a third clock signal having a third frequency based on the second clock signal. The first frequency multiplier includes a circuit configured to control a duty cycle of the first clock signal, a delay circuit configured to receive the duty controlled clock signal, and delay the received signal based on a duty cycle of the second clock signal to output a first delay clock signal, and an XOR gate configured to perform an XOR computation using the duty controlled clock signal and the first delay clock signal to output the second clock signal. The second frequency is greater than the first frequency, and the third frequency is greater than the second frequency.

Techniques, systems and architectures for generating desired phase shifts in a phased array to control the directions of radiation in a wide range of angles are disclosed. Particularly, phased array architectures based on novel PLL-coupled phase shifting techniques for implementation in millimeter-wave (mm-wave) and sub-terahertz (sub-THz) operations range are described. In one aspect, a phased array including an array of unit cells is disclosed. In some embodiments, each unit cell in the array of unit cells includes a dual-nested PLL that is configured to effectuate phase locking and frequency locking to a reference signal from an adjacent unit cell. Moreover, each PLL includes control circuitry that can generate a wide range of phase shifts between adjacent unit cells to facilitate phased-array operations. Note that using the dual-nested PLL to generate a desired phase shift between adjacent radiating elements eliminates the use of conventional lossy phase shifters in the phased array.

A method of frequency search and error correction of clock and data recovery circuit, comprising: initializing a frequency search algorithm parameter; processing a frequency error parameter UP/DN signals according to the set algorithm parameter and starting the frequency search, in which, the algorithm accordingly counts the UP/DN signals. When a phase error signal transition occurs, a transition parameter JUMP is accumulated by 1, and an accumulation parameter SUM is obtained and is further judged that whether a frequency search result is to be output. Number of repeating times of verification and threshold parameters are set, accordingly a reset DCRL value is obtained to verifies a frequency locking result and outputs the result. The present invention improves accuracy of UP/DN pulse counting, increases stability and reliability of the frequency locking, avoids a false locking in the frequency locking, and prevents an excessive locking time in the frequency locking, overcomes error judgment of the frequency search caused by a random jitter, and correctly completes the frequency search and locking, avoids failure of the CDR caused by an error frequency locking.

An eye opening monitor device and an operation method thereof are provided. The eye opening monitor device includes a phase interpolator, a first sampling circuit, a second sampling circuit, and a clock centering circuit. The first sampling circuit samples a data signal according to a data clock to generate first sampled data. The second sampling circuit samples the data signal according to a phase interpolation clock to generate second sampled data. The phase interpolator changes a phase of the phase interpolation clock according to a phase interpolation code. The clock centering circuit counts multiple comparison results of the first sampled data and the second sampled data in multiple clock cycles to obtain an error count value for any one of different phase interpolation codes. The clock centering circuit determines the phase interpolation code provided to the phase interpolator based on the error count values corresponding to different phase interpolation codes.

Provided is a phase-locked loop circuit, a method for configuring the same, and a communication device. The phase-locked loop circuit includes a phase-locked loop main circuit and a phase temperature compensation circuit. The phase temperature compensation circuit includes at least one phase delay unit connected to the phase-locked loop main circuit and configured to generate a phase shift as a result of a temperature change for cancelling out a phase shift generated by the phase-locked loop main circuit as a result of a temperature change.

A noise detection circuit includes a first transistor configured to receive a delayed version of a clock signal; a second transistor configured to receive a delayed version of a reference clock signal; and a latch circuit, coupled to the first transistor at a first node and coupled to the second transistor at a second node, and configured to latch logic states of voltage levels at the first and second nodes, respectively, based on whether a timing difference between transition edges of the clock signal and the reference clock signal exceeds a pre-defined timing offset threshold.

A noise detection circuit includes a first transistor configured to receive a delayed version of a clock signal; a second transistor configured to receive a delayed version of a reference clock signal; and a latch circuit, coupled to the first transistor at a first node and coupled to the second transistor at a second node, and configured to latch logic states of voltage levels at the first and second nodes, respectively, based on whether a timing difference between transition edges of the clock signal and the reference clock signal exceeds a pre-defined timing offset threshold.

A method is provided for enhancing the detection of the start time of a reference oscillator (4) of a super-regenerative receiver (1), which includes the reference oscillator, a bias current generator (7), an oscillation detector (6), and an impedance matching unit (3). Following the supply of the bias current (i_vco) after receiving the activation control signal (Sosc), an oscillation detection is performed by the oscillation detector (6), and once oscillation is detected, an additional amplification current (iboost) dependent on the envelope of the detected oscillation, of an amplification current generation circuit is supplied to the reference oscillator (4) in addition to the bias current to amplify the oscillation signal to be above a critical oscillation start threshold so as to precisely define the start time of the oscillator, and enable the oscillation detector (6) to order the stoppage of oscillation of the reference oscillator (4).

An apparatus is disclosed for making circuitry with passive fundamental components more robust. In example implementations, an apparatus includes at least one passive fundamental component and at least one redundant passive fundamental component. The apparatus also includes fault tolerant circuitry coupled to the at least one passive fundamental component and the at least one redundant passive fundamental component. The fault tolerant circuitry includes fault detection circuitry configured to detect a fault of the at least one passive fundamental component. The fault tolerant circuitry also includes component repair circuitry configured to disconnect the at least one passive fundamental component based on the fault.