A semiconductor circuitry includes an oscillator configured to output an oscillation signal whose frequency depends on a first input signal, a counter configured to count a number of cycles of the oscillation signal, first circuitry configured to output a first digital signal based on a first number of cycles counted by the counter within one of a clock cycle of a clock signal, wherein the first input signal is digitally converted into the first digital signal, and a second circuitry configured to output a second digital signal based on a second number of cycles counted by the counter in a period from a reference timing of the clock signal to an input timing of a second input signal within the one of the clock cycle of the clock signal, wherein the period is digitally converted into the second digital signal.

A semiconductor circuitry includes an oscillator configured to output an oscillation signal whose frequency depends on a first input signal, a counter configured to count a number of cycles of the oscillation signal, first circuitry configured to output a first digital signal based on a first number of cycles counted by the counter within one of a clock cycle of a clock signal, wherein the first input signal is digitally converted into the first digital signal, and a second circuitry configured to output a second digital signal based on a second number of cycles counted by the counter in a period from a reference timing of the clock signal to an input timing of a second input signal within the one of the clock cycle of the clock signal, wherein the period is digitally converted into the second digital signal.

A method for providing a reference clock signal, comprising: generating, by an oscillator, a first clock signal having a first frequency, the first clock signal being coupled to a frequency synthesizer; generating, by the frequency synthesizer, a second clock signal based on the first clock signal, the second clock signal having a second frequency different from the first frequency; outputting a reference clock signal to one or more components of an electronic device, the reference clock signal being one of the first clock signal or the second clock signal; identifying one or more spurious frequency components; and monitoring the reference clock signal for a presence of the one or more spurious frequency components, the monitoring comprising: in response to determining the presence of at least one of the one or more spurious frequency components, selecting a different one of the first clock signal or the second clock signal to be the reference clock signal.

The data recovery from sub-carriers gradients (DRSG) of a received OFDM signal affected by deterministic and random distortions introduced by a transmission link, contributes a method and a circuit for utilizing gradients characterizing shapes of OFDM sub-carriers comprised in such OFDM signal for recovering data symbols transmitted originally.

The data recovery from sub-carriers gradients (DRSG) of a received OFDM signal affected by deterministic and random distortions introduced by a transmission link, contributes a method and a circuit for utilizing gradients characterizing shapes of OFDM sub-carriers comprised in such OFDM signal for recovering data symbols transmitted originally.

A clock generating device, a controller and a storage device. The clock generating device comprises: a clock generator counter outputting a clock trigger signal according to a clock period of each reference number of a reference clock; a compensation counter module outputting a compensation signal, the compensation counter module comprises: a first compensation counter outputting a first compensation clock according to a clock period of each first compensation number of the reference clock, the first compensation number is greater than the reference number, the compensation signal includes the first compensation clock; and a clock generator, when the compensation signal is in a first state, the clock generator generates a target clock signal according to the clock trigger signal; when the compensation signal is in a second state, the clock generator cancels a corresponding pulse in the clock trigger signal according to the compensation signal to generate the target clock signal.

A clock generating device, a controller and a storage device. The clock generating device comprises: a clock generator counter outputting a clock trigger signal according to a clock period of each reference number of a reference clock; a compensation counter module outputting a compensation signal, the compensation counter module comprises: a first compensation counter outputting a first compensation clock according to a clock period of each first compensation number of the reference clock, the first compensation number is greater than the reference number, the compensation signal includes the first compensation clock; and a clock generator, when the compensation signal is in a first state, the clock generator generates a target clock signal according to the clock trigger signal; when the compensation signal is in a second state, the clock generator cancels a corresponding pulse in the clock trigger signal according to the compensation signal to generate the target clock signal.

An example frequency converter includes a drift canceling loop with a balanced delay and a linear signal path (e.g., linear with respect to frequency scaling, amplitude modulation, and/or phase modulation). One side of the drift canceling loop includes a fixed delay, and the opposite side includes an adjustable, complementary delay. The adjustable, complementary delay facilitates precision matching of the signal delays on each side of the loop over a range of frequencies, which results in a significant improvement in noise cancelation, particularly at large offsets to the carrier, while permitting the use of a higher noise, but very fast tuning course scale oscillator. The linear signal path from the signal generator to an RF output facilitates modulation of the signal by the signal generator. A modular format is an advantageous embodiment of the invention that includes the removal of the frequency synthesizer's low phase noise reference into a separate module.

An example frequency converter includes a drift canceling loop with a balanced delay and a linear signal path (e.g., linear with respect to frequency scaling, amplitude modulation, and/or phase modulation). One side of the drift canceling loop includes a fixed delay, and the opposite side includes an adjustable, complementary delay. The adjustable, complementary delay facilitates precision matching of the signal delays on each side of the loop over a range of frequencies, which results in a significant improvement in noise cancelation, particularly at large offsets to the carrier, while permitting the use of a higher noise, but very fast tuning course scale oscillator. The linear signal path from the signal generator to an RF output facilitates modulation of the signal by the signal generator. A modular format is an advantageous embodiment of the invention that includes the removal of the frequency synthesizer's low phase noise reference into a separate module.

A circuit and corresponding method control cycle time of an output clock used to clock at least one other circuit. The circuit comprises an agile ring oscillator (ARO) and ARO controller. The ARO includes at least one instance of a first ring oscillator (RO) and second RO that generate high and low phases, respectively, of cycles of the output clock. The ARO controller controls durations of the high and low phases, independently, via first and second control words output to the ARO, respectively. In a present cycle of the output clock, the ARO controller effects a change to the high or low phase, or a combination thereof, in a next cycle of the output clock by updating the first or second control word, or a combination thereof, based on an indication of expected usage of the at least one other circuit in the next cycle. The change improves a performance-to-power ratio of the at least one other circuit.