A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.

The present invention provides an ADC for receiving at least an input signal to generate a digital output signal, wherein the ADC includes an input terminal and a plurality of output terminals, the input terminal is arranged to receive the input signal, and each of the output terminals is configured to output one bit of the digital output signal. The ADC is controlled to operate in a normal mode or a low power mode, and when the ADC operates in the normal mode, all of the output terminals are enabled to output the bits to form the digital output signal; and when the ADC operates in the low power mode, only a portion of the output terminals are enabled to output the bits to form the digital output signal.

Aspects of the subject disclosure may include, for example, a device that encodes digital signals representing image data captured by a video camera and provided according to a 4K ultra-high definition (4K-UHD) standard. The digital signals are transmitted as serial digital interface (SDI) streams to a wavelength-division multiplexing (WDM) unit; the WDM unit performs electrical-to-optical conversion of the SDI streams and outputs a multiplexed signal to a single fiber-optic cable. The video camera, encoding unit, and WDM unit form a combined module within a housing; the device connects to a proximal end of a single fiber-optic cable, and a distal end of the single fiber-optic cable is configurable for connection to a demultiplexer of a 4K-UHD video presentation device. The multiplexed signal is transmitted on the single fiber-optic cable unidirectionally from the proximal end to the distal end. Other embodiments are disclosed.

The present application relates to a reconfigurable analog front-end circuit and a reconfigurable Ethernet transceiver with a reconfigurable analog front-end circuit. The circuit is reconfigurable using the at least one signal-path switching element controlled by a mode signal to operationally establish a first or a second signal path. The first signal path comprises an optional first signal-conditioning section and a shared ADC. The second signal path comprises an optional second signal-conditioning section, an upstream ADC and the shared ADC. The signal paths are selectively switched in response to a mode signal.

A first analog signal may be sampled during a first time period in accordance with a first sampling range and a sampling resolution step size, where a first digital sequence may be outputted during the first time period based on sampling the first analog signal.

Embodiments of the present disclosure include a microcontroller with a processor core, memory, and a plurality of peripheral devices including a differential digital delay line analog-to-digital converter (ADC). The ADC includes differential digital delay lines and circuit comprising a set of delay elements included in the differential digital delay lines configured to generate data representing an analog to digital conversion of an input. The microcontroller also includes a digital comparator coupled with an output of the ADC and an associated register, wherein at least one output of the digital comparator is configured to directly control another peripheral of the plurality of peripherals.

This disclosure relates to an analog-to-digital converter, ADC. The ADC comprises a first detection and second detection line, each including a plurality of serially arranged detection units, where the detection units of the first line are controlled in accordance with a first signal and the detection units of the second line are controlled in accordance with a second signal, and each line comprises a first group of serially arranged detection units and a second group of serially arranged detection units, a pulse generator for generating a periodic pulse signal that is fed to each of the lines, a sampling unit configured to read out values held by the detection units of the first group in one of the first and second lines on occurrence of a pulse of the pulse signal reaching a predetermined detection unit of the other one of the first and second lines, and a detection line control unit configured to adjust a delay of the second group of detection units in the one of the first and second lines in accordance with a read out of the detection units of the first group of detection units.

The present application relates to a reconfigurable analog front-end circuit and a reconfigurable Ethernet transceiver with a reconfigurable analog front-end circuit. The circuit is reconfigurable using the at least one signal-path switching element controlled by a mode signal to operationally establish a first or a second signal path. The first signal path comprises an optional first signal-conditioning section and a shared ADC. The second signal path comprises an optional second signal-conditioning section, an upstream ADC and the shared ADC. The signal paths are selectively switched in response to a mode signal.

The resolution of a successive approximation analog-to-digital converter is varied in a wide range. Provided is a successive approximation analog-to-digital converter including a digital-to-analog converter that generates an analog voltage based on a digital code, a comparator to which the analog voltage as the output of the digital-to-analog converter is inputted, a DAC control circuit that generates the digital code of an input voltage sampled from an external clock signal by successively changing the digital code based on the output of the comparator, a delay circuit that starts the determination of the comparator by signal transition generated by delaying the signal state change of the output of the comparator, a clock generation circuit that generates a signal starting the determination of the comparator, and a selector circuit that selects a signal generated by the delay circuit or a signal generated by the clock generation circuit to feed the selected signal to the comparator.

An analog to digital converting circuit includes a correlated double sampling circuit (CDS) that compares a pixel signal with a ramp signal, and outputs a comparison signal, a timing amplifier that increases an active time of the comparison signal N times, and outputs an extended signal, wherein the N is a positive integer, and a counter that outputs a digital signal corresponding to the pixel signal in response to the extended signal and a first clock signal.