A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.

The resolution of a successive approximation analog-to-digital converter is varied in a wide range. Provided is a successive approximation analog-to-digital converter including a digital-to-analog converter that generates an analog voltage based on a digital code, a comparator to which the analog voltage as the output of the digital-to-analog converter is inputted, a DAC control circuit that generates the digital code of an input voltage sampled from an external clock signal by successively changing the digital code based on the output of the comparator, a delay circuit that starts the determination of the comparator by signal transition generated by delaying the signal state change of the output of the comparator, a clock generation circuit that generates a signal starting the determination of the comparator, and a selector circuit that selects a signal generated by the delay circuit or a signal generated by the clock generation circuit to feed the selected signal to the comparator.

Aspects of the subject disclosure may include, for example, a device that encodes digital signals representing image data captured by a video camera and provided according to a 4K ultra-high definition (4K-UHD) standard. The digital signals are transmitted as serial digital interface (SDI) streams to a wavelength-division multiplexing (WDM) unit; the WDM unit performs electrical-to-optical conversion of the SDI streams and outputs a multiplexed signal to a single fiber-optic cable. The video camera, encoding unit, and WDM unit form a combined module within a housing; the device connects to a proximal end of a single fiber-optic cable, and a distal end of the single fiber-optic cable is configurable for connection to a demultiplexer of a 4K-UHD video presentation device. The multiplexed signal is transmitted on the single fiber-optic cable unidirectionally from the proximal end to the distal end. Other embodiments are disclosed.

A differential digital delay line analog-to-digital converter (ADC) includes differential digital delay lines, a circuit including a set of delay elements included in the differential digital delay lines, and another circuit including another set of delay elements included in the differential digital delay lines. The first circuit is configured to generate data representing an analog to digital conversion of an input. The second circuit is configured to calibrate a source to the differential digital delay lines.

A digital-to-analog converter device including a set of components, each component included in the set of components including a number of unit cells, each unit cell being associated with a unit cell size indicating manufacturing specifications of the unit cell is provided by the present disclosure. The digital-to-analog converter device further includes a plurality of switches, each switch included in the plurality of switches being coupled to a component included in the set of components, and an output electrode coupled to the plurality of switches. The digital-to-analog converter device is configured to output an output signal at the output electrode. A first unit cell size associated with a first unit cell included in the set of components is different than a second unit cell size associated with a second unit cell included in the set of components.

Aspects of the subject disclosure may include, for example, a device that encodes digital signals representing image data captured by a video camera and provided according to a 4K ultra-high definition (4K-UHD) standard. The digital signals are transmitted as serial digital interface (SDI) streams to a wavelength-division multiplexing (WDM) unit; the WDM unit performs electrical-to-optical conversion of the SDI streams and outputs a multiplexed signal to a single fiber-optic cable. The video camera, encoding unit, and WDM unit form a combined module within a housing; the device connects to a proximal end of a single fiber-optic cable, and a distal end of the single fiber-optic cable is configurable for connection to a demultiplexer of a 4K-UHD video presentation device. The multiplexed signal is transmitted on the single fiber-optic cable unidirectionally from the proximal end to the distal end. Other embodiments are disclosed.

Aspects of the subject disclosure may include, for example, a device that encodes digital signals representing image data captured by a video camera and provided according to a 4K ultra-high definition (4K-UHD) standard. The digital signals are transmitted as serial digital interface (SDI) streams to a wavelength-division multiplexing (WDM) unit; the WDM unit performs electrical-to-optical conversion of the SDI streams and outputs a multiplexed signal to a single fiber-optic cable. The video camera, encoding unit, and WDM unit form a combined module within a housing; the device connects to a proximal end of a single fiber-optic cable, and a distal end of the single fiber-optic cable is configurable for connection to a demultiplexer of a 4K-UHD video presentation device. The multiplexed signal is transmitted on the single fiber-optic cable unidirectionally from the proximal end to the distal end. Other embodiments are disclosed.

Embodiments of the present disclosure include a differential digital delay line analog-to-digital converter (ADC), comprising differential digital delay lines including series coupled delay cells, wherein a delay time of a first delay line is controlled by a first input of the ADC and a delay time of a second delay line is controlled by a second input of the ADC. The ADC includes a pair of bypass multiplexers coupled at a predefined node location in the series coupled delay cells, latches each coupled with the series coupled delay cells, a converter circuit coupled with the plurality of latches configured to convert data from the latches into an output value of the ADC, and logic circuits configured to select data from the series coupled delay cells to the latches depending on a selected resolution of the differential digital delay line analog-to-digital converter.

An apparatus for interpolating between a first signal edge and a second signal edge is provided. The apparatus includes a plurality of interpolation cells coupled to a common node. At least one of the plurality of interpolation cells is configured to supply, based on a control word, the first signal edge and/or the second signal edge to the common node. Further, the apparatus includes a control circuit configured to activate all of the plurality interpolation cells in a first mode of operation, and to deactivate part of the plurality of interpolation cells in a second mode of operation.

The present disclosure relates to an analog-to-digital converter (ADC) and a method for controlling an ADC. The ADC includes a plurality of quantization levels for analog-to-digital conversion. The ADC is adapted for utilizing a subset of the plurality of quantization levels for analog-to-digital signal conversion. The subset is formed by selecting at least one level to be deactivated using a greedy search method and deactivating the at least one level. The method includes using a subset of the plurality of quantization levels for analog-to-digital signal conversion, the subset being formed by selecting at least one level to be deactivated using a greedy search method and deactivating the at least one level.