The present invention provides a device for processing digital signals. The device comprises a digital signal source and a converter circuit having a current supply. The digital signal source outputs a codeword. The converter circuit receives the codeword from the digital signal source, receives a current at the current supply, and generates an output signal based on the codeword. The device generates the current based on the codeword.

Methods and systems for power amplification of time varying envelope signals are disclosed herein. In one embodiment, a plurality of signals with constant envelope generated from the decomposition of the quantized version of a time varying envelope signal are individually amplified and then summed to form a desired time-varying envelope signal. Amplitude, phase and frequency characteristics of one or more of the constituent signals are controlled to provide the desired phase, frequency, and/or amplitude characteristics of the desired time varying envelope signal. In another embodiment, a time-varying envelope signal is decomposed into in-phase and quadrature components that are quantized and decomposed into a plurality of quasi constant or constant envelope constituent signals. The constituent signals are amplified, and then summed to construct an amplified version of the original time-varying envelope signal. The signal amplifiers may be Class A, B, AB, C, D, Class F or Class S amplifiers to provide high amplification efficiency.

The present disclosure relates to a time-interleaved ADC circuit. The time-interleaved ADC circuit comprises an input for an analog input signal, a first ADC bank comprising a first plurality of parallel time-multiplexed ADCs, wherein the first plurality of parallel time-multiplexed ADCs is configured to subsequently generate a first plurality of samples of the analog input signal during a first time interval, a first buffer amplifier coupled between the input and the first ADC bank. The time-interleaved ADC circuit further comprises a second ADC bank comprising a second plurality of parallel time-multiplexed ADCs, wherein the second plurality of parallel time-multiplexed ADCs is configured to subsequently generate a second plurality of samples of the analog input signal during a second time interval, wherein the first and the second time intervals are subsequent time intervals, a second buffer amplifier coupled between the input and the second ADC bank. The first ADC bank has associated therewith a first dummy sampler, wherein the ADC circuit is configured to activate the first dummy sampler before the start of the first time interval. The second ADC bank has associated therewith a second dummy sampler, wherein the ADC circuit is configured to activate the second dummy sampler before the start of the second time interval.

The present invention provides a receiving circuit, wherein the receiving circuit includes a first ADC, an attenuator, a second ADC, a harmonic generation circuit and an output circuit. In the operations of the receiving circuit, the first ADC performs an analog-to-digital operation on an analog input signal to generate a first digital output signal, the attenuator reduces strength of the analog input signal to generate an attenuated analog input signal, the second ADC performs the analog-to-digital operation on the attenuated analog input signal to generate a second digital input signal, the harmonic generation circuit generates at least one harmonic signal according to the second digital input signal, and the output circuit deletes a harmonic component of the first digital input signal by using the at least one harmonic signal to generate an output signal.

Various embodiments of the present technology may comprise methods and apparatus for an amplifier circuit. Methods and apparatus for an amplifier circuit according to various aspects of the present invention may be utilized in a digital-to-analog converter. The amplifier circuit may comprise a first operational amplifier with a feedback circuit. The feedback circuit may comprise an inverting amplifier circuit.

Techniques for monitoring a distortion signal of a power amplifier circuit, where the output of a distortion monitoring circuit includes little or no fundamental signal and closely represents the actual distortion of the amplifier circuit of a wired communications system. The power amplifier circuit can generate a distortion feedback signal that does not affect the power amplifier's output power capability, e.g., no inherent loss in the fundamental output of the amplifier. That is, using a distortion monitor circuit, the power amplifier circuit can resolve a distortion feedback signal from the intended output signal of the output power amplifier circuit.

Various embodiments of the present technology may comprise methods and apparatus for an amplifier circuit. Methods and apparatus for an amplifier circuit according to various aspects of the present invention may be utilized in a digital-to-analog converter. The amplifier circuit may comprise a first operational amplifier with a feedback circuit. The feedback circuit may comprise an inverting amplifier circuit.

A digital-to-analog converter comprises a plurality of first digital-to-analog converter cells configured to generate a first analog signal based on first digital data, wherein the first digital-to-analog converter cells of the plurality of first digital-to-analog converter cells are coupled to a first output node for coupling to a first load. Further, the digital-to-analog converter comprises a plurality of second digital-to-analog converter cells configured to generate one or more second analog signals based on second digital data, wherein the second digital-to-analog converter cells of the plurality of second digital-to-analog converter cells are coupled to one or more second output nodes, and wherein the plurality of first digital-to-analog converter cells and the plurality of second digital-to-analog converter cells are coupled to a power supply node for coupling to a mutual power supply.

A method and apparatus for decomposition of signals with varying envelope into offset components are disclosed here, that sample the time variant envelope of a single carrier (SC) or a multi-carrier (MC) band limited signal, quantizes the sampled value using N.sub.b quantization bits and decomposes the sample into N.sub.b in-phase and quadrature components that are combined in pairs and modulated to generate a set of N.sub.b offset signals. The pulse shape applied in each offset signal is selected according to the spectral mask needed for the signal and to minimize envelope fluctuations in each offset signal from the set of N.sub.b components.

Described herein are DACs with low distortion for high dynamic range (HDR), extremely high dynamic range (EHDR), and other suitable applications. Some embodiments relate to a device including a DAC configured for coupling to an amplifier via a force path and a sense path. For example, the DAC may provide output current to the amplifier via the force path, and the DAC may sense the input voltage of the amplifier via the sense path. Accordingly, distortion such as harmonic distortion and/or gain offset from parasitic impedances in the force and/or sense paths may be reduced or eliminated. Some embodiments relate to a DAC including a voltage reference generator configured to compensate for variations in impedances of the DAC, such as due to semiconductor process variation. Accordingly, distortion in the DAC output due to variations in the DAC impedances may be reduced or eliminated.